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1. WO2003001595 - DISPOSITIF ELECTRONIQUE

Numéro de publication WO/2003/001595
Date de publication 03.01.2003
N° de la demande internationale PCT/IB2002/002579
Date du dépôt international 25.06.2002
CIB
H01L 23/485 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
23Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
48Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
482formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées
485formées de structures en couches comprenant des couches conductrices et isolantes, p.ex. contacts planaires
CPC
H01L 2224/04042
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
H01L 2224/05093
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05075Plural internal layers
0508being stacked
05085with additional elements, e.g. vias arrays, interposed between the stacked layers
05089Disposition of the additional element
05093of a plurality of vias
H01L 2224/05556
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0555Shape
05556in side view
H01L 2224/05558
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0555Shape
05556in side view
05558conformal layer on a patterned surface
H01L 2224/05599
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
H01L 2224/45015
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
45001Core members of the connector
4501Shape
45012Cross-sectional shape
45015being circular
Déposants
  • KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL/NL]; Groenewoudseweg 1 NL-5621 BA Eindhoven, NL
Inventeurs
  • COLLETTE, Daniel; NL
Mandataires
  • GROENENDAAL, Antonius, W., M.; Internationaal Octrooibureau B.V. Prof. Holstlaan 6 NL-5656 AA Eindhoven, NL
Données relatives à la priorité
09/887,44425.06.2001US
Langue de publication anglais (EN)
Langue de dépôt anglais (EN)
États désignés
Titre
(EN) ELECTRONIC DEVICE
(FR) DISPOSITIF ELECTRONIQUE
Abrégé
(EN)
The electronic device comprises a bond pad structure with a bond pad (14), an underlying metal layer (18) and a passivation layer (20) extending between the metal layer (18) and the bond pad (14), wherein the passivation layer (20) is perforated beneath the bond pad (14). Preferably, the perforations (34) are hexagonal to produce a hexagonal matrix. To reduce or avoid deformation of the matrix during bonding, the hexagons are oriented relative to the bond pad axis, for example at 15 degrees.
(FR)
L'invention concerne un dispositif électronique qui présente une structure de plot de connexion composée d'un plot de connexion (14), d'une couche métallique sous-jacente (18) et d'une couche de passivation (20) s'étendant entre la couche métallique (18) et le plot de connexion (14), cette couche de passivation (20) étant perforée au-dessous du plot de connexion (14). De préférence, les perforations (34) sont hexagonales de façon que la matrice soit hexagonale. Afin de réduire ou d'éviter la déformation de la matrice pendant la connexion, les hexagones sont orientés par rapport à l'axe du plot de connexion, par exemple à 15 degrés.
Également publié en tant que
RU2004107898
Dernières données bibliographiques dont dispose le Bureau international