Traitement en cours

Veuillez attendre...

PATENTSCOPE sera indisponible durant quelques heures pour des raisons de maintenance le samedi 31.10.2020 à 7:00 AM CET
Paramétrages

Paramétrages

Aller à Demande

1. WO2001080302 - PROCEDE D'ASSEMBLAGE D'UNE PUCE A PROTUBERANCES

Numéro de publication WO/2001/080302
Date de publication 25.10.2001
N° de la demande internationale PCT/JP2001/003183
Date du dépôt international 13.04.2001
Demande présentée en vertu du Chapitre 2 11.10.2001
CIB
H01L 21/56 2006.01
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
21Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
02Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
04les dispositifs présentant au moins une barrière de potentiel ou une barrière de surface, p.ex. une jonction PN, une région d'appauvrissement, ou une région de concentration de porteurs de charges
50Assemblage de dispositifs à semi-conducteurs en utilisant des procédés ou des appareils non couverts par l'un uniquement des groupes H01L21/06-H01L21/326185
56Capsulations, p.ex. couches de capsulation, revêtements
CPC
H01L 21/563
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
H01L 2224/13109
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
13001Core members of the bump connector
13099Material
131with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
13101the principal constituent melting at a temperature of less than 400°C
13109Indium [In] as principal constituent
H01L 2224/16225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
H01L 2224/29007
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
29001Core members of the layer connector
29005Structure
29007Layer connector smaller than the underlying bonding area
H01L 2224/29111
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
29001Core members of the layer connector
29099Material
291with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
29101the principal constituent melting at a temperature of less than 400°C
29111Tin [Sn] as principal constituent
H01L 2224/2919
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
28Structure, shape, material or disposition of the layer connectors prior to the connecting process
29of an individual layer connector
29001Core members of the layer connector
29099Material
2919with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
Déposants
  • NAMICS CORPORATION [JP]/[JP] (AllExceptUS)
  • SUZUKI, Osamu [JP]/[JP] (UsOnly)
  • YOSHII, Haruyuki [JP]/[JP] (UsOnly)
  • SUZUKI, Kenichi [JP]/[JP] (UsOnly)
Inventeurs
  • SUZUKI, Osamu
  • YOSHII, Haruyuki
  • SUZUKI, Kenichi
Mandataires
  • TSUKUNI, Hajime
Données relatives à la priorité
2000-11308114.04.2000JP
Langue de publication japonais (JA)
Langue de dépôt japonais (JA)
États désignés
Titre
(EN) FLIP CHIP MOUNTING METHOD
(FR) PROCEDE D'ASSEMBLAGE D'UNE PUCE A PROTUBERANCES
Abrégé
(EN)
A method of mounting a flip chip not allowing voids to be produced between a semiconductor chip and a substrate, comprising at least either of the steps of (A) drying the substrate, (B) (1) dispensing uncured sealant at least at a bump pressing portion on the surface of the substrate and/or the entire portion of the substrate where minute irregularities are present, and (B)(2) performing a pressing and the curing of the sealant while maintaining the temperature conditions so that a temperature difference between the semiconductor chip and the substrate does not cause a convection substantially in the uncured or curing sealant.
(FR)
L'invention concerne un procédé d'assemblage d'une puce à protubérances, qui ne laisse pas de vide entre une puce à semi-conducteur et un substrat, et qui comprend au moins l'une des étapes consistant à: (A) sécher le substrat, (B) (1) appliquer un matériau d'étanchéité non durci au moins sur une des parties appuyant contre une bosse à la surface du substrat et/ou sur toute la surface du substrat sur laquelle se trouvent de petites irrégularités, et (B) (2) comprimer et durcir le matériau d'étanchéité, tout en maintenant les conditions de température de sorte que la différence de température entre la puce à semi-conducteur et le substrat ne provoque pas de convection sensible dans le matériau d'étanchéité non durci ou en train de durcir.
Également publié en tant que
Dernières données bibliographiques dont dispose le Bureau international