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1. WO1997018591 - ARCHITECTURE DE CELLULE DE CIRCUIT INTEGRE ET SYSTEME DE TRACES D'INTERCONNEXION

Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

[ EN ]

WHAT IS CLAIMED IS:

1. A circuit layout architecture for integrated circuits using cells comprising:
a plurality of substantially rectangular basic cells disposed in rows along a first direction, each one of said basic cells including a P-type diffusion region and an N-type diffusion region for transistor source and drain terminals, at least a first gate electrode region for transistor gate terminals, said at least first gate electrode region bridging between said P-type diffusion regions and said N-type
diffusion regions in a second direction transverse to said first direction, and contact regions for making electrical contact to said diffusion regions and said gate electrode region;
wherein a macro cell is formed by interconnecting adjacent basic cells and wherein interconnections internal to said macro cell are made using interconnect lines from a first conductive layer and a second conductive layer;
wherein input/output terminals of a plurality of said macro cells are selectively coupled together via first, second and third groups of global interconnect lines;
said first group of global interconnect lines being formed from said first conductive layer and disposed along said first direction;
said second group of global interconnect lines being formed from said second conductive layer above said first conductive layer, and disposed along said first direction; and said third group of global interconnect lines being formed from a third conductive layer above said second
conductive layer, and disposed transverse to said first direction along said second direction.

2. The circuit layout architecture of claim 1, wherein adjacent ones of said rows alternately mirror one another.

3. The circuit layout architecture of claim 1, wherein an orthogonal power grid for supplying power and ground to said macro cells is formed from said first
conductive layer interconnect lines along said first direction and from said third conductive layer interconnect lines along said second direction, and wherein said second conductive layer couples between selected regions of said first
conductive layer.

4. The circuit layout architecture of claim 1, wherein said p-type diffussion region and said n-type
diffusion region are laid out in a non-rectangular shape.

5. The circuit layout architecture of claim 4 , wherein each of said plurality of basic cells comprises said first gate electrode region having a first electrode and a second gate electrode region having a second electrode, said first gate electrode having a first end and a opposing second end, said first end at a contact region at an indentation in said P-type active diffusion region, said second end having no contact region adjacent said N-type active diffusion region, said first gate electrode having contact at an intermediate contact region, and said second gate electrode having a third end and an opposing fourth end, said third end at a contact region at an indentation in said N-type active diffusion region, said fourth end having no contact region adjacent said P-type active diffusion region, said second gate electrode having contact at an intermediate contact region, each one of which is shared between said P-type active diffusion region and said N-type active diffusion region.

6. The circuit layout architecture of claim 1, wherein each of said plurality of rectangular basic cells has first and second substrate contact regions disposed in
corners .

7. The circuit layout architecture of claim 5, wherein each of said plurality of basic cells comprises contact regions for source and drain contacts disposed along a common axis with said first end contact region and said third end contact region for gate electrodes in said first
direction.

8. The circuit layout architecture of claim 6, wherein each of said plurality of basic cells comprises at least one contact region for source and drain contacts
disposed along a common axis with substrate contact regions in said first direction.

9. The circuit layout architecture of claim 1, wherein said substantially rectangular basic cell has a first dimension along said second direction accessible by a group of not more than ten global interconnect lines of said first conductive layer.

10. The circuit layout architecture of claim 9, wherein said substantially rectangular basic cell has a second dimension in said first direction accessible by no more than four global interconnect lines of said third conductive layer.

11. The circuit layout architecture of claim 5, wherein said first and second gate electrode regions form a first and second transistors in each one of said first P-type diffusion region and said N-type diffusion region, and wherein said P-type diffusion region extends to form a PMOS
transistor.

12. The circuit layout architecture of claim 11, wherein said N-type diffusion region extends to define an NMOS transistor.

13. The circuit layout architecture of claim 6, wherein said substrate contact regions are shared between selected ones of said basic cells which are disposed adjacent to each other in said second direction.

14. The circuit layout architecture of claim 1, wherein a first interconnect line from said first conductive layer makes contact to an interconnect line from said second conductive layer immediately above said first interconnect line forming a double -layer parallel interconnect line to reduce resistance.

15. The circuit layout architecture of claim 6, wherein a first group of said plurality of basic cells is disposed adjacent to each other to form a first row of basic cellε, and a second group of said plurality of basic cells is disposed adjacent to each other to form a second row of basic cells;
wherein said first row is disposed above said second row such that a P-type diffusion region in a basic cell within said first row is placed laterally adjacent to a P-type diffusion region in a basic cell within said second row; and
wherein an interconnect line from said first layer at least twice the minimum width of an interconnect line from said first layer extends in the first direction over said substrate contact regions in basic cells of both said first and second rows .

16. The circuit layout architecture of claim 3, wherein said second conductive layer couples interconnect lines of said first conductive layer to interconnect lines of said third conductive layer.

17. The circuit layout architecture of claim 1, wherein said second group of global interconnect lines couples to said input/output terminals only along said first
direction.

18. A basic cell for arrangement in rows for use in an integrated circuit using cells comprising:
a P-type active diffusion region having a non-rectangular outline;
an N-type active diffusion region having a non-rectangular outline;
a first gate electrode extending across said P-type and N-type active diffusion regions in a first direction separating source contact regions and drain contact regions of a first PMOS transistor and separating source contact regions and drain contact regions of a first NMOS transistor,
respectively;
a second gate electrode extending across said P-type and N-type active diffusion regions in said first direction separating source contact regions and drain contact regions of a second PMOS transistor and separating source contact regions and drain contact regions of a second NMOS transistor, respectively, said first gate electrode having a first end and a opposing second end, said first end at a contact region at an indentation in said P-type active diffusion region, said second end having no contact region adjacent said N-type active diffusion region, said first gate electrode having contact at an intermediate contact region, and said second gate electrode having a third end and an opposing fourth end, said third end at a contact region at an indentation in said N-type active diffusion region, said fourth end having no contact region adjacent said P-type active diffusion region, said second gate electrode having contact at an intermediate contact region.

19. The basic cell of claim 18 further comprising:
a substrate contact region and first active
diffusion contact region,
wherein an overall shape of the cell is
substantially defined by a rectangle with a first dimension along said first direction and a second dimension along a second direction, and wherein said substrate contact region is disposed along the same axis as said first active diffusion contact region in said second direction, and said gate electrode contact region is disposed along the same axis as said
substrate contact region in said second direction.

20. The basic cell of claim 19 wherein said
substrate contact region further comprises a first substrate contact region and a second substrate contact region each disposed in corners of said rectangle.

21. The basic cell of claim 20 wherein a length of said first dimension is substantially defined by nine second-layer interconnect lines extending in parallel in said second direction, and a length of said second dimension is
substantially defined by three third- layer interconnect lines extending in said first direction.

22. The basic cell of claim 18, wherein first metal interconnect lines are made from a first conductive layer and are disposed in a second direction transverse to said first direction and wherein second metal interconnect lines are made from a second conductive layer over said first conductive layer in said second direction, and wherein third interconnect lines are made from a third conductive layer over said second conductive layer and are disposed in said first direction.

23. The basic cell of claim 18, wherein, in said first direction, each said P-type active diffusion region comprises at least four active diffusion contact regions in a central section, two active diffusion contact regions in a first lateral region separated by said first gate electrode, and at least three active diffusion contact regions in a second lateral region separated by said second gate electrode.

2 . A method of designing an integrated circuit using cells comprising:
providing a plurality of substantially rectangular basic cells disposed in rows along a first direction, each one of said basic cells including a P-type diffusion region and an N-type diffusion region for transistor source and drain terminals, at least a first gate electrode region for
transistor gate terminals, said at least first gate electrode region bridging between said P-type diffusion regions and said N-type diffusion regions in a second direction transverse to said first direction, and contact regions for making
electrical contact to said diffusion regions and said gate electrode region;
forming a macro cell by interconnecting adjacent basic cells and wherein interconnections internal to said macro cell are made using interconnect lines from a first conductive layer and a second conductive layer;
selectively coupling input/output terminals of a plurality of said macro cells together via first, second and third groups of global interconnect lines;
forming said first group of global interconnect lines from said first conductive layer and disposed along said first direction;
forming said second group of global interconnect lines from said second conductive layer above said first conductive layer, and disposed along said first direction; and forming said third group of global interconnect lines from a third conductive layer above said second
conductive layer, and disposed transverse to said first direction along said second direction.

25. A circuit layout architecture for an integrated circuit using cells, said circuit layout architecture
comprising:
a cell having a first pair of PMOS and NMOS
transistors and a second pair of PMOS and NMOS transistors, said first and second pairs placed adjacent to each other in a first direction and each transistor having a gate electrode extended substantially in a second direction, said second direction being substantially perpendicular to said first direction;
a first interconnect line made from a first
conductive layer for making interconnections inside said cell in said first and said second direction;
a second interconnect line made from a second conductive layer above said first conductive layer and
separated from said first conductive layer by an insulating layer, said second interconnect line for making
interconnections internal and external to said cell in said first direction.

26. The circuit layout architecture according to claim 25 wherein said cell has a substantially rectangular shape with a first dimension along said first direction defined by a maximum of three contact regions, and a second dimension along said second direction defined by a maximum of nine contact regions .

27. The circuit layout architecture of claim 26 wherein said cell with substantially rectangular shape further comprises first and second substrate contact regions disposed in corners .

28. A method of designing an integrated circuit layout using cells, comprising the steps of:
(a) forming a cell by laying out a first pair of PMOS and NMOS transistors adjacent to a second pair of PMOS and NMOS transistors in a first direction, each of said transistors having a gate electrode being extended
substantially in a second direction, said second direction being substantially perpendicular to said first direction;
(b) making interconnections internal to said cell with a first interconnect line made from a first conductive layer, said first interconnect line being used in said first direction and said second direction; and (c) making interconnections internal and external to said cell with a second interconnect line made from a second conductive layer above said first conductive layer, and separated from said first conductive layer by an insulating layer, said second interconnect line being used in said second direction.

29. An integrated circuit using cells comprising:
a first group of global interconnect lines made from a first conductive layer and disposed along a first direction;
a second group of global interconnect lines made from a second conductive layer above said first conductive layer, and disposed along said first direction;
a third group of global interconnect lines made from a third conductive layer above said second conductive layer, and disposed along a second direction substantially different than said first direction; and
a plurality of basic cells, each one including diffusion regions for transistor source and drain terminals, gate electrode regions for transistor gate terminals, and contact regions for making electrical contact to said
diffusion and gate electrode regions,
wherein, a macro cell is made by interconnecting adjacent basic cells, and interconnections internal to a macro cell are made using interconnect lines from said first and second conductive layers, and
wherein, said plurality of macro cells are
selectively coupled together via said first, second and third group of global interconnect lines,
wherein each one of said plurality of basic cells comprises a first diffusion region of a first type and a second diffusion region of a second type, and wherein said first and second diffusion regions are laid out in a non-rectangular shape,
wherein each of said plurality of basic cells comprises a first and second gate electrode regions, each one of which is shared between a transistor made in said first diffusion region and a transistor made in said second
diffusion region,
wherein each of said plurality of basic cells has a substantially rectangular shape with a first and second substrate contact regions disposed in corners, and
wherein said substantially rectangular shape of each of said plurality of basic cells has a first dimension defined by a maximum of nine interconnect lines made from said first conductive layer disposed in parallel in said first direction, and a second dimension defined by at least three interconnect lines made from said third conductive layer disposed in parallel in said second direction.

30. The integrated circuit of claim 29, wherein said first dimension is made larger to add at least a tenth interconnect line to form at least ten interconnect lines made from said first conductive layer and disposed in said first direction, said first and second diffusion regions being separated by a minimum width of two of said at least ten interconnect lines .

31. The circuit layout architecture of claim 29 wherein said cell with substantially rectangular shape further comprises first and second substrate contact regions disposed in corners .

32. The circuit layout architecture of claim 31 wherein said cell comprises three columns of contact regions extending along said first direction, and wherein contact regions from a first and a third column are used to connect to gate electrodes for said PMOS and NMOS transistors.

33. A circuit block for use in an integrated circuit constructed of circuit blocks comprising:
a P-type diffusion region and an N-type diffusion region for transistor source and drain terminals oriented in parallel along a first direction, at least a first gate electrode region for transistor gate terminals, said at least first gate electrode region bridging between said P-type diffusion regions and said N-type diffusion regions in a second direction transverse to said first direction, and contact regions for making electrical contact to said
diffusion regions and said gate electrode region;
wherein a macro cell is formed by interconnecting adjacent transistors and wherein interconnections internal to said macro cell are made using interconnect lines from a first conductive layer;
wherein input/output terminals of a plurality of said macro cells are selectively coupled together via first, second and third groups of global interconnect lines;
said first group of global interconnect lines being formed from said first conductive layer and disposed along said first direction;
said second group of global interconnect lines being formed from said second conductive layer above said first conductive layer, and disposed along said first direction; and said third group of global interconnect lines being formed from a third conductive layer above said second
conductive layer, and disposed transverse to said first direction along said second direction.

34. The cell of claim 33, wherein an orthogonal power grid for supplying power and ground to said macro cells is formed from said first conductive layer interconnect lines along said first direction and from said third conductive layer interconnect lines along said second direction, and wherein said second conductive layer couples between selected regions of said first conductive layer.

35. The cell of claim 34, wherein said p-type diffusion region and said n-type diffusion region are laid out in a non-rectangular shape.

36. The cell of claim 35, wherein said first gate electrode region has a first electrode and a second gate electrode region has a second electrode, said first gate electrode has a first end and a opposing second end, said first end at a contact region at an indentation in said P-type active diffusion region, said second end having no contact region adjacent said N-type active diffusion region, said first gate electrode having contact at an intermediate contact region, and said second gate electrode having a third end and an opposing fourth end, said third end at a contact region at an indentation in said N-type active diffusion region, said fourth end having no contact region adjacent said P-type active diffusion region, said second gate electrode having contact at an intermediate contact region, each one of which is shared between said P-type active diffusion region and said N-type active diffusion region.

37. The cell of claim 33, further having first and second substrate contact regions disposed in corners .

38. The cell of claim 37, wherein a first said cell is disposed adjacent to another said cell to form a first group of basic cells, and a second said cell is disposed adjacent to still another said cell to form a second group of basic cells;
wherein said first group is disposed above said second group such that a P-type diffusion region in a basic cell within said first group is placed laterally adjacent to a P-type diffusion region in a basic cell within said second group; and
wherein an interconnect line from said first layer at least twice the minimum width of an interconnect line from said first layer extends in the first direction over said substrate contact regions in basic cells of both said first and second groups .