Recherche dans les collections de brevets nationales et internationales
Certains contenus de cette application ne sont pas disponibles pour le moment.
Si cette situation persiste, veuillez nous contacter àObservations et contact
1. (WO1995034913) TRANSISTORS A EFFET DE CHAMP A GRILLE AMORCEE ET CIRCUITS COMPRENANT CES TRANSISTORS
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

BOOTSTRAPPED-GATE FIELD EFFECT
TRANSISTORS AND CIRCUITS THEREOF

RELATED FIELD OF THE INVENTION
This invention relates to semiconductor field effect transistors and in particular, to semiconductor field effect transistors utilized as electronically variable resistance sources or
attenuators.

BACKGROUND OF THE INVENTION
Field Effect Transistors (FETs) are widely utilized for providing variable resistance in
electronic circuits such as radio frequency (RF) or microwave frequency (MF) attenuation circuits and continuous time filters, etc.
In those circuits, to be attenuated input AC signal is applied, for example, to a FET's source terminal, and the attenuated signal is provided at its drain terminal. The input signal is thus attenuated by the resistance between the source and drain of the FET; such resistance is controlled by the voltage applied to the FET's gate terminal. Consequently., the FET functions as a voltage controlled variable resistor.
The principle of using FETs to provide variable resistance is well known; it is briefly described as follows using a conventional n-channel GaAs MEtal Semiconductor Field Effect Transistor ("GaAs MESFET") illustrated in Figs. 1A-C.
Referring to Fig. 1A, a conventional n-channel GaAs MESFET has an n-doped GaAs epitaxial layer 105 deposited on a semi-insulating GaAs
substrate 100, source and drain regions 120 and 125 formed in GaAs layer 105, and contacts 121 and 124 formed on the source and drain regions, respectively. A gate metallization 115 is deposited on GaAs layer 105 and between the source and drain contacts, which forms with the GaAs layer a Schottky diode having a depletion region 110. A region 102 between the depletion region and the semi-insulating substrate is defined as the channel region.
The source-to-drain resistance is defined as the resistance between the source and drain contacts. Because the source-to-drain resistance of the above-described MESFET is mainly determined by the channel resistance which is controlled a voltage applied to the gate, we use the term "channel resistance"
hereinafter to refer the source-to-drain resistance. Varying the gate voltage changes the depletion region and the channel region thickness and thus the channel resistance. The channel or depletion region thickness is referred hereinafter as their dimensions along the direction perpendicular to the substrate.
Fig. lb illustrates a typical output
characteristic of a GaAs MESFET. In this figure, IDS and VDS represent drain-to-source current and voltage, respectively. Each of the curves represents IDS versus Vus at a particular gate voltage, VG. For each curve, at low VDS, IDS approximately linearly increases with Vøs; the slope of the curve corresponds to the drain-to-source resistance at a specific gate voltage and such resistance varies with the gate voltage. At a fixed gate voltage such as VGι, however, if VDS
increases beyond Vr^i, IDS begins to saturate, i.e., it changes little when VDS increases more.
Fig. 1C shows an equivalent circuit diagram for a FET used as a variable resistance source. The FET is shown as a variable resistor RDS; signal to be attenuated, V,, is connected to one end of the variable resistor; a load, VLOAD, is connected to the other end of the resistor.
Ideally, FET's channel resistance depends only on the gate voltage. In practice, however, it depends not only on the gate voltage but also on the input signal. As a result, the output signal is undesirably distorted, i.e., the waveform of the output signal is distorted as compared with the waveform of the input signal. This distortion, called FET's nonlinearity or nonlinear distortion, limits FETs' applications in many RF and microwave control circuits which require high linearity. This has been the subjects in many technical discussions and
publications, e.g., in Caverly, "Distortion in broad-band gallium arsenide MESFET control and switch circuits," IEEE Trans. Microwave Theory Tech.. 39(4), pp. 713-717 (April 1991), and in Gutmann et al., "Characterization of linear and nonlinear properties of GaAs MESFET's for broad-band control applications," IEEE Trans. Microwave Theory Tech.. 35(5), pp. 516-520, (May 1987) .
Several mechanisms are identified as causing nonlinear distortion in FETs. First, the FET's current saturation characteristic, shown in Fig. IB, causes distortion. Referring again to Figs. IB and 1C, if Vfc is greater than VDS1, the transistor will partially operates in the nonlinear portion of the IDS curves. As a result of the drastic change of the channel resistance value at or about V^V^i, the attenuation to the input signal suddenly changes at Vda=VDSι and nonlinear distortion occurs. Even though this kind of distortion may be reduced by limiting the input signal's amplitude to less than V^, such limitation is impractical because it greatly reduces the power the FET can handle. Conventional GaAs MESFETs exhibit significant nonlinearity even at a power level less than 5 dbm. See, for example, the measurement of MPFET, AGC FET, and DBS FET shown in Fig. 7C, representing measurement for Anadigics' Medium Power Field Effect Transistors ("MPFET"),

Automatic Gain Control Field Effect Transistors ("AGC FET") , and Direct Broadcast Satellite Field Effect Transistors ("DBS FET"), respectively.
Moreover, VDS1, the drain-to-source voltage at which the current begins to saturate, is not a constant and it changes with the gate voltage. VDSι is approximately expressed in the following equation (See, e .g. , Sze , "Physics of semiconductor devices," A Wiley-Interscience Publication, p.318, 1981)


where VP is the transistor's pinch-off voltage and it depends only on the doping
concentration and the geometric dimensions of the transistor, VG is the gate voltage, and VBI is the internal bias voltage between the gate and the channel and it is normally fixed once the transistor is fabricated. Therefore, VDSι linearly depends on the gate voltage.
Second, although ideally the channel resistance should depend only on the voltage applied to the gate terminal, in practice the channel
resistance also depends on the input AC signal. Input AC signal modulates the depletion region thickness and as a result, effects the channel resistance. Suppose the input signal Vs is applied to the source of a

MESFET and the drain is grounded, the depletion region thickness, d, at the source end is generally described as
d= [ 2 es ( VS+VG+VBI) /qNd] m ( 2 ) where e, is the permittivity of the channel
semiconductor material, V, is the input signal, VG is the gate voltage, q is the elementary charge, and Nd is the doping concentration in the channel, assuming the doping concentration is uniform. (See Sze , "Physics of semiconductor devices, " A iley-Interscience
Publication, p.312-318, 1981) The channel resistance is thus approximated as
Rds«L/{qμnNd(h-d) } (3) where Rj. is the channel resistance, L is the channel length, μn is the electron mobility in the channel (assuming the channel is doped n-type) , h is the n-GaAs layer thickness, and W is the channel width.
Because, as shown in equation (2) , channel resistance Rj. depends on the depletion region thickness, d, which in turn depends on the input signal V,, shown by equation (2) , the channel resistance R^ also depends the input signal, which results in nonlinear
distortion. Note that this kind of distortion occurs even if the FET operates on the liner portion of its current output characteristic.
Because of their nonlinear distortion, conventional FETs are not suitable for use in circuits that require high linearity and low distortion;
consequently, PIN diodes are normally employed instead of FETs in high linearity circuits.
Various circuit techniques have been
developed to reduce FETs' nonlinear distortion.
Dolby, in U.S. Patent No. 4,786,879, disclosed an active circuitry which detects the FET's source-drain voltage. If the voltage exceeds a predetermined value, the active circuitry then provides feedback a portion of the output signal to its input.
Consequently, the source-drain voltage is reduced to less than the predetermined value within which the FET operates in the linear portion of the output current characteristics.
Although Dolby circuit reduces distortion due to FETs' current saturation, it has several limitations. First, this technique only addresses the distortion due to the current saturation, it has no effect on the distortion due to the depletion region modulation by the input signal. Second, because this technique requires active circuitry, it will be difficult and costly to monolithically integrate this FET and the active circuitry with other circuits.
U.S. patent No. 4,574,249 to Williams is directed to transimpedance amplifier circuits; it also described a transimpedance amplifier using a four terminal FET as a variable feedback resistor. The FET is either a conventional MOSFET type or a p-n-p silicon JFET illustrated in Fig. ID. The Williams ' s FET includes, besides source and drain terminals, a gate terminal at the source end (Gl) and another gate terminal at the drain end (G2) , and it operates by applying a differential DC voltage, i.e., Vj,.+ΔV and ΔV, to Gl and G2, respectively. By creating a DC differential gate voltage along the channel, Williams attempts to offset the channel thickness non-uniformity caused by a DC source-to-drain bias, thus maintaining a uniform gate-to-channel DC voltage along the channel.
However, William would not significantly reduce nonlinear distortion because, although the gate-to-channel DC voltage may be uniform in
Williams ' s FET, the channel thickness is still
affected by input AC signal. As a result, channel resistance varies with the input AC signal and
nonlinear distortion occurs. Further, as depicted in Fig. ID, the thickness of depletion region 130 between the gate and channel may be kept uniform, the
thickness of a depletion region 140 between the N-channel and the P-type Si substrate is still
uncontrolled. Consequently, the thickness of
depletion region 140 and thus the channel resistance varies with the input signal, and distortion occurs. Moreover, this FET requires at least two DC voltage supplies for biasing the gate, making its application more expensive and less convenient.
In U.S. patent application No.07/845,293 which is assigned to the common entity as this
application, Scheinberg disclosed a variable
resistance circuit using an externally bootstrapped FET. As shown in Fig. 2, the variable resistance circuit 200 consists of a FET 205 having its gate and source connected by a capacitor C its gate and drain connected by another capacitor C2, and its gate coupled to a control voltage VG through a resistor.
The variable resistance circuits operates as follows: Because the slow-varying gate control voltage VG is coupled to FET's gate 210 though
resistor R, gate 210 is effectively floated with respect to AC signal. Accordingly, capacitors Cj and C2 impose additional AC signal at the gate, and the voltage at the gate partially follows the input signal. As seen from equations (1) and (2), this reduces the dependency of depletion region thickness on the input signal and reduces the distortion. In addition, as seen from equation (1) , because VDS1 depends on VG and VG partially follows the input signal v«> VDSI also partially follows the input signal. As a result, distortion due to the current saturation is also reduced.
However, this bootstrapped circuit has several limitations. First, the circuit is only capable to feedback a portion of the input signal to the gate; the ratio of this portion to the input signal is approximately C2/(C,+C2). For the reasons of symmetry, C, and C2 normally have equal values, which results feedback of 50% of the input signal to the gate. It would be desirable to feedback more than 50% of the input signal to the gate to further reduce the distortion. Second, although this circuit does not use active circuit component to suppress distortion, it still requires external components like resistors and capacitors, which makes it difficult and costly for monolithically integration.

SUMMARY OF THE INVENTION
The first aspect of the present invention is directed to field effect transistors for providing electronically controllable resistance with high linearity and low distortion. In accordance with a first embodiment, a field effect transistor ("FET") comprises channel, source and drain regions formed in a semiconductor layer deposited on a substrate having a substantially higher resistivity than the channel region, and a resistive gate region disposed over the channel region. Advantageously, the resistive gate region provides, with respect to the channel region, distributed resistance and capacitance. The
distributed resistance and capacitance provide
distributed feedback of input AC signal to the gate region. As a result, the dynamic channel resistance of the FET is substantially independent of the input AC signal.
In a preferred embodiment, a FET comprises a n-type GaAs layer deposited on a semi-insulating GaAs substrate. N-type source and drain regions are formed in the n-GaAs layer, defining therebetween a channel region. A resistive gate region made of resistive material such as cermet is deposited on the channel region. The resistive gate region provides, with respect to the channel region, distributed resistance and capacitance.
Another preferred embodiment is in the form of a junction field effect transistor ("JFET") , comprising an n-type GaAs layer disposed on a semi-insulating GaAs substrate and a p-type GaAs resistive gate region formed in the n-type GaAs layer. Source and drain regions are formed in the n-type GaAs layer. The gate region provides, with respect to the channel region, distributed resistance and capacitance.
In accordance with a second embodiment, a

JFET comprises a semiconductor resistive gate region having a first conductivity type deposited on a substrate, a semiconductor layer having a second conductivity type deposited on the resistive gate region. Source and drain regions are formed in the semiconductor layer, forming therebetween a channel region. The resistive gate region of the JFET
provides, with respect to the channel region,
distributed resistance and capacitance.
A preferred embodiment comprises a p-type implanted GaAs layer, as a resistive gate region, formed on a semi-insulating GaAs substrate and an implanted n-type GaAs layer formed on the resistive gate region. Source and drain regions are formed in the n-type GaAs layer, forming therebetween a channel region.
All of the FETs of the present invention are designated hereinafter as Bootstrapped Gate Field Effect Transistors ("BGFETs") . Thus, we have invented a new type of field effect transistors, BGFETs. The BGFETs are characterized by their resistive gate regions which provide, with respect to the channel regions, distributed resistance and capacitance, and by which the channel is formed on a layer that has a substantial higher resistivity than the channel region; preferably, such layer is a semi-insulating layer or an insulator such as semi-insulating GaAs layer or silicon oxide. During operation, the channel region resistance substantially depends only on a control voltage applied at the gate.
A BGFET may be configured as a three or four terminal devices. A three terminal BGFET is formed by providing a single electrical contact to the resistive gate region. A four terminal BGFET is formed by providing a first gate contact to the portion of the gate region that is close to the source region, and a second gate contact to the portion of the gate region that is close to the drain region. The four terminal BGFET offers additional flexibility over a
conventional FET in biasing the BGFET in that a bias voltage may be applied between the first and second gate contacts of the four terminal BGFET.
A second aspect of the present invention relates to an electronically variable resistance circuit comprising an externally bootstrapped BGFET. The electronically variable resistance circuit has input, output and control terminals, and it comprises a BGFET of the present invention coupled to an
external bootstrap circuit. For three terminal BGFET, the external bootstrap circuit comprises a first capacitive means coupled between the gate and source terminals of the BGFET, a second capacitive means coupled between the gate and drain terminals of the BGFET, and a resistive means coupled between the gate terminal of the BGFET and the control terminal of the circuit. The input terminal of the circuit is coupled to the source terminal of the BGFET; the output terminal of the circuit is coupled to the drain terminal of the BGFET. This variable resistance circuit provides low distortion, high linearity attenuation, to input AC signal. Moreover, this circuit can be used to provide attenuation for AC signal having frequencies lower than the BGFET's own low frequency limit.
For the four terminal BGFET having a source terminal, a drain terminal, a first gate terminal at the source end and a second gate terminal at the drain end, the variable resistance circuit comprises a first capacitive means coupled between the source and first gate terminals, a second capacitive means coupled between the drain and the second gate terminal; a first resistive means is coupled between the control terminal and the first gate terminal; a second
resistive means is coupled between the control terminal and the second gate terminal. The input and output terminals of the variable resistance circuit are connected to the source and drain terminals of the BGFET, respectively.
Another aspect of the present invention relates to attenuation circuit that utilizes the
BGFETs of the present invention. In particular, the attenuation circuits include τr-type attenuation circuits and T-type attenuation circuits.

BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects, features and advantages of the invention will be more apparent from the following detailed description in conjunction with the appended drawings in which:

Figs. 1A-C illustrate a cross-sectional view, output characteristics, and an equivalent circuit diagram of a prior art GaAs MESFET,
respectively;
Fig. ID shows a FET in William;
Fig. 2 shows a variable resistance circuit consisting of a FET and a bootstrapping circuit externally coupled to the FET;
Fig. 3A depicts a cross-sectional view of a first preferred embodiment of Bootstrapped-Gate Field Effect Transistors ("BGFETs") of the present
invention;
Fig. 3B illustrates a three-dimensional view of the first preferred embodiment;
Fig. 3C depicts, for the sole purposes of demonstrating the operating principle of the BGFETs, an equivalent circuit of a BGFET;
Fig. 3D illustrates a device symbol for a three-terminal BGFET;
Figs. 3E and F depict a cross-sectional view of a four-terminal BGFET and its device symbol, respectively.
Fig. 4A depicts a three-dimensional view of a second preferred embodiment of BGFETs of the present invention;
Figs. 4B and 4C illustrate the cross-sectional views of three-terminals and four terminal embodiments of the BGFET of Fig. 4A;
Fig. 5A illustrates a three-dimensional view of a third referred embodiment of the BGFETs;
Figs. 5B and 5C illustrate the cross-sectional views of three-terminals and four terminal embodiments of the BGFET of Fig. 5A;
Fig. 6A illustrates a three-dimensional view of a second embodiment of the BGFETs;

SUBSTITUTESHEET(RULE25) Fig. 6B shows a top view of an alternative embodiment of the BGFET of Fig. 6A;
Fig. 6C depicts the cross-section of an alternative embodiment to the BGFET of Fig. 6A;
Fig. 6D shows a topical view of a multi-fingered BGFET;
Fig. 7A illustrates a three-dimensional view of another embodiment of BGFETs of present invention;
Figs. 7B and 7C show the test results for the BGFET of Fig. 7A;
Fig. 7D shows the circuit diagram for a circuit utilized in testing the BGFETs;
Fig. 8 shows the test results of the circuit of Fig. 7D;
Figs. 9A-C illustrate more test results of

BGFETs;
Figs. 10A-B illustrate two electronically variable resistance circuits of the present invention; and
Figs. 11A-B illustrate attenuation circuits utilizing BGFETs of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

I. BOOTSTRAPPED FIELD EFFECT TRANSISTORS
In accordance with a first aspect of the invention, a bootstrapped gate field effect transistor (BGFET) comprises source, drain and channel regions disposed on a semiconductor substrate layer, and a resistive gate region disposed over the channel region. Preferably, the substrate layer has a substantially higher resistivity than the channel region. The resistive gate region provides, with respect to the channel region, distributed resistance and capacitance. Advantageously, in response to AC signal applied at the source or drain, the distributed resistance and capacitance provides distributed AC feedback voltage to the resistive gate region. The distributed AC feedback substantially cancels the effect of the input AC signal on the channel
resistance, thus suppressing nonlinear distortion.

1. First Embodiment
1.1 First Preferred Embodiment
As shown in Fig. 3A, a first preferred embodiment comprises a semi-insulating GaAs substrate 300 and an implanted n-type GaAs layer 301 formed on the substrate. A resistive gate region 320 is
deposited on n-type GaAs layer 301. Source and drain regions 310 and 315, respectively, are formed in the expitaxial layer by ion-implantation of n-type dopant. Since the resistive gate region forms with epitaxial layer 301 a Schottky diode, a depletion region 335 is established between gate region 320 and layer 301. A channel region 305 is thus defined as the region between the source and drain regions, and between the depletion region and the substrate.

Source contact 325, drain contact 330, and gate contact 321 are formed on the source, drain, and gate regions, respectively, for providing electrical contacts to the source, drain, and gate regions.
Those contacts consist of metallization layers.
The resistive gate region consists of resistive materials. Cermet such as Cr-SiOx can be used to form the resistive gate region; the
resistivity of Cr-SiOx can be adjusted by changing the ratio of Cr to SiOx in the cermet material.
Referring to Fig. 3B, resistive gate region 320 provides, with respect to channel region 305, distributed resistance and capacitance. Such
distributed resistance and capacitance is
illustratively shown as the resistor and capacitor network 330. The contacts to the source, drain, and gate regions are not shown in this drawing for simplicity.
In this preferred embodiment, the substrate 300 is a semi-insulating GaAs substrate. The
substrate refers to the semiconductor layer that is directly beneath the channel region. In general, the BGFETs of the first embodiment prefer substrates that have a substantially higher resistivity than that of the channel region, thus ensuring that the channel thickness is not affected by the variation of the voltage between the channel region and the substrate. More specifically, the channel thickness is only affected by a single junction, the junction between the gate and channel regions. Because of the
substantially higher resistivity of the substrate, the effect to the channel thickness by the junction between the channel region and the substrate is negligible. As will be apparent from the following discussion, the effect of the input signal on the depletion thickness is reduced by the distributed feedback to the gate region which is provided by the distributed resistance and capacitance. In the preferred embodiment, because of the distributed feedback as well as the substantially higher
resistivity substrate, the effect of the input signal on the channel region is suppressed and nonlinear distortion is substantially reduced.
Referring to Fig. 3C, for the sole purpose of illustrating operation principle of the distributed feedback, the transistor of Fig. 3A is considered as being equivalent to four externally bootstrapped FETs serially connected along their source-to-drain path. The four FETs are designated as T1-T4. Each gate of the FETs is bootstrapped by two capacitors, C, and is connected to a slow varying gate voltage VG via a resistor, R. The capacitors, C, are intended to simulate the distributed capacitance between the resistive gate and channel. The resistors, R, are attributed to the distributed resistance of the resistive gate region.
When AC signal, Vd, is applied to the drain, and the source connects to the ground potential, an AC feedback voltage is generated at each gate of the transistors, T1-T4, due to the bootstrap capacitors and resistors. In particular, the feedback voltage at the gate of transistor Tl is approximated as Vd/8; at transistor T2 is about (3Vd)/8; at transistor T3 is about (5Vd)/8; and at transistor T4 is about and
(7Vd)/8. Due to the effect of resistors R, the potentials at the gate of each transistor floats with respect to AC voltages.
As indicated in the BACKGROUND OF THE
INVENTION, in a conventional FET, the depletion thickness non-uniformity caused by input signal Vd is most severe at the drain end of the channel and least sever at the source end of the channel.
Advantageously, the AC feedback voltage at the gate of FET T4 which is the nearest to the drain, is the greatest, and the feedback voltage at the gate of FET Tl which is the farthest to the drain, is the
smallest; the feedback voltage monotonically decreases from the gate of T4 to the gate of Tl. The non-uniformity of depletion region caused by the input signal, which, without the feedback, would decrease from the drain end to the source end, is thus
compensated by the distributed feedback voltages, V,-V4.
Another significant advantage of the BGFETs over conventional FETs is that the distortion due to the FET's current saturation in its output
characteristics is also greatly reduced or eliminated. Because of the distributed feedback, the channel thickness becomes uniform and is independent of the input AC signal at the source or drain of the BGFET. The depletion region pinch-off due to the input AC signal is thus eliminated. As discussed in the
BACKGROUND OF THE INVENTION, the depletion region pinch-off which causes current saturation is one of the major mechanisms responsible for distortion. The elimination of the depletion region pinch-off at the drain eliminates the distortion due to the current saturation. In other words, due to the distributed feedback and the lack of depletion region between the channel and substrate, the input RF signal applied to the source or drain of the BGFET does not see the current saturation, even though the BGFET still displays such characteristics in its DC
characteristics.

Note that, in order to obtain effective distributed feedback, the input AC signal frequency needs to be greater than a cutoff frequency of the distributed resistance and capacitance. The cutoff frequency is expressed as fc=l/(2πτ) where τ is the time constant of the distributed resistance and capacitance and it is expressed as τ= RECE where RE and CE are the equivalent feedback resistance and capacitance the BGFET.
In the transistor shown in Fig. 3A, there is only a single gate contact 321 which covers
substantially the entire gate region. A device symbol for this type three-terminal BGFET is illustrated in Fig. 3D. Although the gate terminal is illustratively shown in Fig. 3D as closer to the source terminal than the drain terminal, it is not intended to indicate that the gate terminal is located closer to the source; rather, it merely represents that this
transistor utilizes a single gate contact to the resistive gate region.
Alternatively, as illustrated in Fig. 3E, electrical contact to the gate is accomplished by forming a first gate contact 322, designated as Gs, at the source end of the transistor, and a second gate contact 323, designated as GD, at the drain end of the transistor. Because the resistive gate region
comprises resistive material, a voltage may be applied to Gs between GD. Thus, in this configuration, the transistor becomes a four terminal device. Gs and GD can also be externally connected with a conductor so that the transistor be used as a three-terminal device.
Fig. 3F illustrates a device symbol of this device. It includes a source terminal, S, a drain terminal, D, a gate terminal at the source end, Gs , and a gate terminal at the drain end, GD. The
resistor between Gs and GD represent the distributed gate resistance along the channel. As explained in detail in the proceeding paragraphs, when applying an alternating signal to the source or drain of the device, the distributed resistance and capacitance of the transistor imposes a distributed feedback voltage on the gate region. Such feedback voltage is not uniform across the gate; rather, it is distributed along the channel. Consequently, the feedback at Gs and GD is different.
Because the fabrication process for the above described BGFETs is similar to that for
convention GaAs MESFETs, this BGFET can be integrated into GaAs monolithic microwave circuits.
In the above described BGFETs, the
semiconductor layer containing the channel region is formed on a semi-insulating substrate. Alternatively, as well known to those skilled in the art, the
semiconductor layer may also be formed on a semi-insulating or non-doped expitaxial buffer layer which is in turn formed on a substrate. This device
functions to suppress the distortion the same way as the preferred embodiment.
The above described preferred embodiment employs GaAs material and technology. Similar
transistor can also be made utilizing silicon material and technology. In making the silicon transistors, preferably, a silicon epitaxial layer is first
deposited on a silicon dioxide substrate or a sapphire substrate, followed by the formation of the drain, source, and resistive gate regions. Contacts to those regions are subsequently made. The resistive gate region is made of either cermet, lightly doped
polysilicon, or other kinds of resistive material. As well known to those skilled in the art, other
semiconductor materials may also be utilized for making transistors that operate on the basis of the same principle to suppress distortion as the above-described preferred embodiment.

1.2 Second Preferred Embodiment
Fig. 4A illustrates a three dimensional view of a second preferred embodiment. This BGFET
comprises a Si02 substrate 400, an epitaxial p-type silicon layer 401 formed on the substrate, an silicon gate oxide layer 410 formed on layer 401, and a resistive gate region 415 deposited on the silicon oxide layer. N-type source region 420 and drain region 425 are formed in p-type Si layer 401. Thus, a channel region 405 is established under the gate Si02 layer and between the source and drain regions.
Advantageously, the resistive gate region provides, with respect to the channel region distributed resistance and capacitance which is illustratively shown as a resistor and capacitor network 430. The resistance in the distributed resistance and
capacitance is mainly due to the resistance of the resistive gate material; the capacitance is mainly due to the capacitance between the resistive gate and the channel. This device has a similar structure as that of a conventional silicon MOSFET; however, the gate of this BGFET comprises resistive material instead of metal conductor as in the case of MOSFET, and the substrate is an insulating Si02 substrate.
Contacts to the source, drain, and gate regions can be similarly made as that of the first embodiment. Referring to Fig. 4B, by forming a single gate contact 418 that covers substantially the entire gate region 415, and source and drain contacts 419 and 424, a three terminal BGFET is established.
Alternatively, referring to Fig. 4C, a four terminal BGFET can be constructed by, in addition to the contacts to the source and drain regions, forming a first gate contact 416, designated as Gs, at the source end and a second gate contact 417, designated as GD, at the drain end.

1.3 Third Preferred Embodiment
A cross-sectional view of a third preferred embodiment is illustrated in Fig. 5A. This BGFET is a type of a GaAs Junction Field Effect Transistor (JFET) wherein a pn junction is utilized to modulate the channel resistance. The BGFET comprises a semi-insulating GaAs substrate 500 and an n-type GaAs layer 506 deposited on the substrate. Two heavily doped n-regions, 525 and 530, are formed in layer 506 as source and drain regions, respectively. A lightly doped p-type GaAs resistive gate region 510 is formed in layer 506 and between the source and drain regions. The p-type GaAs resistive gate region and n-type GaAs layer 506 adjacent the gate region constitute a pn junction having a depletion region designated as 515, defining a channel region 505 between the depletion region and the substrate.
The distributed resistance and capacitance is illustratively shown as the resistor and capacitor network 520. The distributed resistance is mainly due to the resistance of the gate region and the
distributed capacitance due to the capacitance of the pn junction.
One way to fabricated this GaAs BGFET is to first form an n-type GaAs epitaxial layer on a semi-insulating GaAs substrate, followed by photo-lithography and an implantation of n-type dopants defining the source and drain regions, and another photo-lithography and an implantation of p-type dopants to form the resistive gate. Preferably, the doping concentration of the source or drain region is equal or higher than 1018/cm3 for making low resistance contact. In this transistor, the resistivity of the resistive gate region can be adjusted by changing the dose of the implanted dopant in the resistive gate region.
The device with similar structure can also be made with silicon material. For example, a Si02 or sapphire substrate may be utilized as the substrate; the source and drain and channel regions are made of n-type silicon material, and the resistive gate is made of p-type silicon material.
Figs. 5B and 5C depict the three-terminal and four-terminal BGFETs based on this embodiment.

2. SECOND EMBODIMENT
2.1 First Preferred Embodiment
Fig. 6A illustrates the cross-sectional view of a BGFET comprising a semi-insulating GaAs substrate 700 and an implanted GaAs resistive gate region 705 having a p-typed conductivity type formed on the substrate. A GaAs channel region 720 having n-type conductivity type is formed on the gate region.
Source and drain regions 710 and 715 having n-type conductivity type are formed.
Two GaAs gate contact regions 725 and 730 having p-type conductivity are formed outside the channel, source and drain regions to control the potential of the gate region. Source and drain contacts 735 and 740 are formed on the source and drain regions, respectively, for providing electrical contact to those regions. Another two contacts 745 and 750, are formed on the gate contact regions 725 and 730, respectively, for providing electrical contact to the gate contact regions. This BGFET has a structure of a side-gate field effect transistor since the gate contacts are formed outside the region that is between the source and drain.
Preferably, this BGFET is formed by first depositing an n-type epitaxial layer on a semi-insulating GaAs substrate, followed by a first p-type ion-implantation to form the gate region. A first n-type implantation is then performed to define the channel. Next, a second n-type ion-implantation and a second p-type ion-implantation are performed to define the source and drain regions, and the gate contact regions, respectively.
In this device, gate region 705 provides, with respect to channel 720 distributed resistance and capacitance. Note that the distributed resistance depends on the dosage of the first p-type implantation as well as the thickness of the gate region; the distributed capacitance depends on both the first p-type implantation that forms the gate region, and the first n-type implantation that forms the channel.
Note that p-channel BGFETs of this kind can be
similarly made by replacing the n-type regions with p-type regions, and p-type regions with n-type regions.
Note that, in this embodiment, the substrate is not in direct contact with the channel region.
Consequently, once the BGFET is fabricated, the channel resistance substantially depends only on the voltage between the resistive gate region and the channel region.
Fig. 6B illustrates a top view of an
alternative BGFET to the one described above. The elements in this figure are similarly designated as those of Fig. 6A for simplicity. In this BGFET, gate contact regions 725 and 730 are not formed alongside source and drain regions 710 and 740, respectively. Compared to the BGFET of Fig. 6A, this embodiment has reduced interaction between gate contact regions and the source or drain region because they are further apart.
Fig. 6C depicts another alternative BGFET to the ones described above. In this BGFET, electrical contact to the gate region is made by forming contacts 745 and 750 disposed over a portion of resistive gate region 705 that is exposed by a mesa.
Fig. 6D illustrates a layout design of a multi-fingered BGFET which has a structure similar to that of Fig. 6A. The BGFET includes a mesa 755 formed on a semi-insulating substrate 773 and interposed source regions 760 and drain regions 765 formed on the mesa. Source and drain contacts 770 and 775 are deposited on an exposed surface of the semi-insulating substrate, each having contacting fingers 772 or 774 extending over an dielectric layer deposited over the mesa. Via holes 771 and 776 are formed in the
dielectric layer, allowing contacting fingers 772 and 774 to make electrical contact to the source and drain regions, respectively. A gate contact 780 is
similarly formed contacting a gate region through via holes 781. A portion 785 of the gate contact is a thin film resistor which is used to further float the gate region with respect to AC voltage.

2.2 Second Preferred Embodiment
Fig. 7A depicts a second preferred
embodiment. This BGFET comprises a semi-insulating GaAs substrate 800, an implanted p-type gate region 805, an implanted n-type channel 820, and implanted n-type source and drain regions 810 and 815. Source and drain contacts 835 and 840 are formed on the source and drain regions, respectively. This transistor is formed on a mesa and it is electrically isolated from other devices on the substrate.
Gate contacts 845 are formed partially on top of the mesa and partially on the substrate, and it covers at least a portion of the side of the mesa. As a result, gate contacts 845 directly contact gate region 805 at the side of the mesa.
This BGFET further includes two n-type regions 812 and 815 formed beneath and in contact with the portion of the gate contact that is on the mesa. Those regions are utilized to control the electrical potential of the gate region in case the gate contacts fail to make a good electrical contact to the gate region through the side of the mesa.
This preferred embodiment is fabricated as follows:
A p-type ion-implantation is first performed on a surface of a semi-insulating GaAs wafer to form gate region 805. The surface doping concentration of the p-type ion-implantation is about 6xl012/cm2.
Next, a mesa is defined by a first photolithography and etching. The etching may be conducted by wet chemical etching, reactive ion etching, or other etching techniques.
The channel region is then defined by a second photo-lithography, followed by a first n-type ion-implantation that forms channel region 820. The distance between the source and drain, i.e. the channel length, L, for this transistor, is typically about 5μm; the channel width, W, is approximately lOOμm. The surface doping concentration for the first n-type ion-implantation is approximately 6.5xl012/cm2. Note that the p-type implantation for forming the gate region is conducted on the entire surface of the wafer, whereas the first n-type ion-implantation for the channel region is only performed at the channel region.
Source region 810, drain region 815, and n-type regions 812 and 814 are then photo-lithographically defined, followed by a second n-type ion-implantation. Preferably, for making low serial resistance contact to the source and drain regions, the surface doping concentration for the second n-type ion-implantation is higher than the first n-type ion-implantation.
Gate contacts 845 and source and drain contacts 835 and 840 are subsequently defined by the steps of photo-lithography, deposition of a
metallization alloy layer, liftoff, and thermal annealing. Alternatively, source and drain may be first formed with a first metallization alloy such as AuGe; gate contact are then formed with a second metallization alloys such as AuBe or AuZn which makes low resistance contact to p-type GaAs gate region through the side of the mesa. Those techniques are all well known to those skilled in the art and will not be discussed in detailed here.
Alternatively, the topology of the BGFET can also be arranged similarly as the one illustrated in Fig. 6B. In this case, the gate contacts are formed on the "front" and "back" of the BGFET as in Fig. 6B instead alongside the source and drain regions.
Multi-fingered layout design as illustrated in Fig. ID may also be utilized.
Fig. 7B presents the test result of this BGFET's attenuation versus its gate voltage. In the test, the transistor is used as a series attenuator, i.e. the test signal is applied to the source of the transistor and the output signal is measured at the drain of the transistor. The attenuation is measured at a test signal frequency of 800 MHz. In this figure, the y axis represents the attenuation (in db) to the input signal, and the x-axis corresponds to the voltage applied to the gate. If the pinch off voltage is defined as the gate voltage at which the
attenuation of the transistor is 20 dB, the pinch off voltage of this BGFET is approximately -3V. Referring to the BGFET structure illustrated in Fig. 7A, the pinch off voltage of the BGFET can be adjusted by adjusting the dosage and energy of the implantation that form the n-type channel region and the p-type gate region.
Fig. 7C illustrates the test result of third order intercept point IIP3 (dbm) versus the
attenuation (db) obtained from a two-tone test for the BGFET. As a comparison, third order intercept points for a conventional Medium Power FET ("MPFET") , an implanted conventional Automatic Gain Control FET ("AGC FET"), and an Anadigics1 Distribute Broadcast Satellite FET ("DBS FET"), which are comparable to the resulted disclosed in aforementioned reference Caverly et al . , are also presented in the same drawing. The tests is performed by applying test signal at the source of a FET and measuring the attenuated signal at the drain of the FET.
As discussed in the BACKGROUND OF THE
INVENTION, when a conventional FET is used as a variable resistor in an attenuation circuit or other circuits, it introduces distortion to the waveform of the input signal. Such distortion of waveform is displayed in the frequency spectrum as containing not only the input signal frequency, but also frequencies different from the input signal frequency. In other words, if input signal has a frequency f, the output signal comprises signal having frequency f as well as frequencies different from f. This is also referred to as a transistor's nonlinearity.
In the frequency spectrum, a transistor's nonlinearity mainly consists of two types of
nonlinearity, harmonic frequency nonlinearity and Inter-Modulation ("IM") frequency nonlinearity.
Harmonic frequency nonlinearity refers to unwanted signal having frequencies that are integer times of input signal frequencies; in typical applications, this type of nonlinearity can be easily eliminated with filter circuits. IM nonlinearity refers to unwanted signal having frequencies such as, assuming input signal having frequencies ft and f2, (fj+f2) , (fj-f2) , (2fj+f2) , (2fj-f2) , etc. IM nonlinearity is much more difficult to remove than harmonic frequency nonlinearity.
A two-tone test is a test devised to measure the nonlinearity of electronic devices and circuits such as FETs. In this test, two input signals having equal power P^ but at different frequencies, fj and f2, respectively, are first combined and then applied to the source terminal of the FET under test. The output signal power at frequency f, (or f2) , P-^π, is "then measured. By varying the input signal power Pta and measuring output signal power Po^π, a first curve of pout,fi (dbm) v. Pj,, (dbm) is thus obtained. Next, the output power is measured at one of the inter-modulation frequencies ("IM") , fI; such as (ft-f2)
(assuming f, > f2) , (fj+f2) , (2fj-f2) , (2f]+f2) , or etc. By varying P^ and measuring P^π, a second curve of P^π (dbm) v. Pj,, (dbm) is acquired.

The first and second curves are then plotted in one drawing and the curves are extrapolated towards the higher P;,, region of the drawing where the two curves intercept each other. The output power of signals of the inter-modulation frequency at the point of interception is called intercept point.
A FET's intercept point for inter-modulation frequencies, f,, at (fι+f2) and (fι~f2) is called second order intercept point (IIP2) ; the intercept point for inter-modulation frequencies, flr at (2fj-f2) , (2f2-fj) , (2ft+f2) , and (2f2+fj) are defined as third order intercept point (IIP3) .
The definition and method for obtaining the second or third order intercept point are described in detail in many publications and for example, by G. Heiter in "Characterization of Nonlinearities in
Microwave Devices and Systems," IEEE Transaction on Microwave Theory and Techniques , Vol. MTT-21, No. 112, Dec. 1973, which is incorporated herein by reference.
Intercept point is a useful measure of a device's IM nonlinearity; it is normally independent of the input signal power. Higher value of the intercept point (in dbm) represents less non-linearity in a transistor. In particular, third order intercept point is independent of the test circuit configuration and thus, is a reliable measure of a device's total nonlinearity.
Again referring to Fig. 7C, the vertical axis refers to the third order intercept point, IIP3, in dbm and the horizontal axis the attenuation in db. As shown, over the attenuation range from 5 to 20 db, the third order intercept point of the BGFET is about average 10 dbm better than that of the other types of FETs, which clearly demonstrates that the BGFET has a much better linearity than the others FETs.

Fig. 7D illustrates a test circuit
configuration for measuring BGFET circuit performance. More specifically, B2 is a BGFET for providing
attenuation and Bl is a shunt BGFET that is identical as B2. A first signal source V, provides first AC signal at a frequency of 250 MHz and a second signal source V2 provides second AC signal having a frequency of 255 MHz. Vj and V2 constitute a two-tone signal generator 900, providing AC input signal to source S2 of transistor B2. The AC input signal comprises frequency components of both 250 MHz and 255 MHz with equal power.
The output signal from the circuit is provided from drain D2 of transistor B2, and it is attenuated by transistor B2. Vc is a variable DC voltage source for controlling the attenuation. Four capacitors, Cx, C2, C3, and C4 are utilized in the circuit for isolating DC voltage sources from the AC voltage source.
The operation of the test circuit can be described as follows:
The input signal from two-tone signal generator 900 is provided to drain Ox of transistor Bλ through capacitor C and to source S2 of transistor B2 through capacitor C2. Drain Dt of transistor Bt is biased at +3V by a DC voltage source V^. Variable DC voltage source Vc is connected to the gate of Blf and to source S2 of transistor B2 through a 50K resistor. Vc can be varied from 0V to +3V.
When Vc is set at 0V, transistor Bl is turned off, i .e . transistor Bl exhibits a maximum resistance between its source and drain, whereas transistor B2 is turned on, i .e . transistor B2 displays a minimal resistance or attenuation between its source and drain. As a result, the circuit allows maximum amount of input signal to reach the output terminal through transistor B2. At this moment, the circuit exhibits the least attenuation to the input signal.
When Vc is controlled at +3V, transistor Bl is fully turned on to AC signal and transistor B2 is turned off. Most of the input signal from the two-tone generator is thus shunted to the ground through transistor Bl. At this moment the circuit allows the least amount of the input signal to reach the output terminal because transistor B2 provides a maximum attenuation.
Therefore, varying Vc from 0 to +3V changes the attenuation of the circuit from a minimum to a maximum. Consequently, by varying Vc from 0V to +3V and measuring the intercept point, a plot of intercept point versus the attenuation for the transistor under test is thus obtained.
Fig. 8 shows the BGFETs' circuit performance tested using the circuit of Fig. 7D. The y axis and x axis correspond to second and third order intercept points in dbm and attenuation, respectively. The BGFETs used has the same structure as the one of Fig. 7A except that it has a pinchoff voltage of
approximately -30V. As shown, the circuit's second order intercept point averages more that 60 dbm and the third order intercept point more that 30 dbm.
Figs. 9A-C represent test results for some BGFETs that have similar structures as that of Fig. 8A but with a different pinchoff voltage. For those BGFETs, the surface doping concentration is about 6.5xl012/cm2 for the n-channel regions, and about
4xl012/cm2 for the p-type gate region.
Fig. 9A depicts the attenuation v. the gate voltage for one of those transistors. A pinchoff voltage of -18V is obtained from this Figure.

Fig. 9B depicts the third order intercept point ("IIP3") v. attenuation for those BGFETs which have the same gate width of 10 μm but different gate length of 5, 10, 20, 30 and 40 μm. Each curve in the drawing is labeled by two number written as LxW where L is the channel length and w is the channel width for the particular BGFET which the curve corresponds to. These results show that the BGFETs having greater gate length exhibit less nonlinearity than the BGFETs having shorter gate length.
Fig. 9C exhibits the test results of the second order intercept point ("IIP2") v. attenuation. The BGFETs* IIP2 improves with decreased gate width. A BGFET with L and W of 10 μm and 10 μm, respectively, displays an IIP2 of almost +50 dBm. Measurement of IIP2 v. L reveals that the IIP2 is not dependent on L. At the attenuation of 10 dB, all of the BGFETs exhibit IIP2 greater than 30 dBm.
The above described test results demonstrate excellent low distortion characteristics of the
BGFETs. To the best of applicant's knowledge, similar results have not be achieved in conventional FETs.

II. ELECTRONICALLY VARIABLE RESISTANCE CIRCUITS
As illustrated in Fig. 10A, a preferred electronically variable resistance circuit 920 of the present invention comprises a four terminal
bootstrapped gate field effect transistor (BGFET) 900 having its source terminal, S, coupled to a first gate terminal, Gs, through a capacitor Cs, and its drain terminal, D, coupled to a second gate terminal, GD, through a second capacitor, CD. The BGFET is
described in detail in the above paragraphs and in Figs. 3-10.

The circuit further includes an input signal terminal 925 connected to the source terminal of the BGFET, an output signal terminal 930 connected to the drain terminal of the BGFET, and a resistance control terminal 935 connected to gate terminal Gs via a resistor Rs, and to gate terminal GD via a resistor RD.
Note that in this circuit, both the BGFET's internal distributed resistance and capacitance, and the external resistor Rs and RD and capacitors Cs and CD provide feedback to the FET's gate terminal. The cutoff frequency for the equivalent feedback circuit is expressed as fc=l/(2τrτ). τ is the time constant of the equivalent feedback circuit and it is expressed as τ— RECE where RE and CE are the equivalent resistance and capacitance of the overall bootstrapped circuit. Because T of this circuit is more than that of the BGFET alone, the cutoff frequency for the circuit is thus less than that of a BGFET itself. Consequently, this circuit is able to operate to provide low
distortion attenuation at lower frequencies lower than what would be operated at for a BGFET alone.
Thus, when input AC signal having a
frequency higher than fc is applied to the input terminal and the output signal is provided at the output terminal, the input signal is attenuated by the resistance between the input and output of terminals of this circuit. Due to the feedback provided by the internal distributed resistance and capacitance of the BGFET and the external bootstrap resistors and
capacitors, the attenuation is substantially linear and independent of the input signal.
By properly choosing the values of resistors Rs and RD, and capacitors Cs and CD, and by adjusting the value of the distributed resistance and
capacitance of the BGFET, this variable resistance circuit can be designed to operate in audio frequency range for providing electronically controlled, highly linear attenuation.
Fig. 11B illustrates a similar attenuation circuit utilizing a three terminal BGFET. More specifically, the circuit comprises a three-terminal BGFET 900, a resistor RQ connected between a control terminal 935 and the gate terminal of the BGFET, a first capacitor Cs connected between the gate and source terminals of the BGFET, and a second capacitor CD connected between the gate and drain terminals of the BGFET. The source and drain terminals of the BGFET are connected to an input terminal 925 and an output terminal 930, respectively.

III. OTHER ATTENUATION CIRCUITS
The BGFETs of the present invention can be utilized in circuits where electronically variable resistance is required. Those circuits includes various kinds of RF or microwave attenuation circuits, continuous time filter, etc.
Fig. 12A illustrates a preferred embodiment of a π-type attenuation network using three three-terminals BGFETs, Tl, T2 and T3 of the present
invention. The attenuation of the circuit is
controlled by controlling the voltage applied to the gate terminals of the BGFETs. As it would be well known to those skilled in the art, BGFETs Tl and T3 may be replaced with conventional FETs; or BGFETs Tl, T2, and/or T3 may be replaced with the electronically variable resistance circuit of Figs. 11A or 11B. In addition, BGFETs Tl, T2, and T3 may be replaced with the four-terminal BGFET of the present invention.
Fig. 12B depicts a preferred embodiment of a τ-type attenuation circuit using the three-terminal BGFETs of the present invention. Alternatively, BGFET T2 may be replaced with a conventional FET; or BGFETs Tl, T2, and T3 may be replaced with the electronically variable resistance circuit of Figs. 11A or 11B. In addition, BGFETs Tl, T2 , and T3 may be replaced with the four-terminal BGFET of the present invention.
It will be apparent to those skilled in the art that numerous modifications may be made within the scope of the invention, which is defined in accordance with the following claims or equivalents thereof.