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1. (WO1995034913) TRANSISTORS A EFFET DE CHAMP A GRILLE AMORCEE ET CIRCUITS COMPRENANT CES TRANSISTORS
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WHAT IS CLAIMED IS:

1. A bootstrapped-gate field effect transistor for providing electronically variable resistance comprising:
channel, source, and drain regions formed in a semiconductor layer deposited on a substrate layer having a substantially higher resistivity than said channel region; and
a resistive gate region comprising resistive material disposed over said channel region,
said gate and channel regions forming a junction whereby the source-to-drain resistance being substantially dependent only on said junction, and
whereby said resistive gate region
providing, with respect to the channel region, distributed resistance and capacitance, said
distributed resistance and capacitance providing distributed feedback to said gate region in response to input AC signal applied to said source or drain region, and
whereby the dynamic source-to-drain
resistance to said input signal being substantially independent of said input signal.

2. The transistor of claim 1 further comprising source and drain contacts formed on said source and drain regions, respectively, and a gate contact deposited on said gate region.

3. The transistor of claim 2 further comprising source and drain contacts formed on said source and drain regions, respectively, a first gate contact formed on the portion of said gate region that is close to said source region, and a second gate contact formed on the portion of said gate region that is close to said drain region.

4. The transistor of claim 1 wherein said gate region extends substantially from said source region to said drain region.

5. The transistor of claim 1 wherein said gate region is deposited on said channel region and forms with said channel region a Schottky-type junction, said transistor being a Schottky-type field effect transistor.

6. The transistor of claim 5 wherein said substrate layer is a GaAs semi-insulating substrate layer, said semiconductor layer is a GaAs layer, and said resistive gate region comprises cermet.

7. The transistor of claim 6 wherein said gate region comprises Cr-Si02.

8. The transistor of claim 5 wherein said substrate layer is a silicon oxide substrate, said semiconductor layer is a silicon layer, and said resistive gate region comprises cermet.

9. The transistor of claim 6 wherein said gate region comprises Cr-Si02.

10. The transistor of claim 5 wherein said substrate layer is a silicon oxide substrate, said semiconductor layer is a silicon layer, and said resistive gate region comprises polysilicon.

11. The transistor of claim 1 wherein said gate region is formed on the channel region, and said gate region comprises substantially single crystal semiconductor material and forms with said channel region semiconductor pn junction, said transistor being a junction field effect transistor.

12. The transistor of claim 11 wherein said semiconductor layer and gate region are GaAs layers having first and second conductivity types,
respectively, and the substrate layer is a GaAs semi-insulating semiconductor substrate layer.

13. The transistor of claim 11 wherein said semiconductor layer and gate region are silicon layers having first and second conductivity types,
respectively, and said substrate layer is a silicon oxide semiconductor substrate layer.

14. The transistor of claim 11 wherein said semiconductor layer and gate region are silicon layers having first and second conductivity types,
respectively, and said substrate layer is a sapphire substrate.

15. The transistor of claim 1 further comprising an insulating layer interposed between the gate region and the channel region.

16. The transistor of claim 15 wherein said semiconductor layer is a silicon layer, and said insulating layer is a silicon oxide layer.

17. The transistor of claim 16 wherein said substrate layer is a silicon oxide substrate layer.

18. The transistor of claim 16 wherein said substrate layer is a sapphire substrate layer.

19. The transistor of claim 16 wherein said resistive gate region comprises cermet.

20. The transistor of claim 19 wherein said resistive gate region comprises Cr-Si02.

21. The transistor of claim 15 wherein said semiconductor layer is a silicon layer, and said insulating layer is a silicon nitride layer.

22. A bootstrapped-gate field effect transistor for providing electronically variable resistance comprising:
channel, source, and drain regions formed in a semiconductor layer deposited on a substrate
semiconductor layer;
a resistive gate region comprising resistive material disposed over said channel region;
source and drain contacts formed on the source and drain regions, respectively, for making ohmic contact thereto; and
a gate contact deposited on said gate region, said gate contact covering substantially the entire said gate region,
whereby distributed resistance and
capacitance being presented between the source and drain regions, said distributed resistance and
capacitance providing distributed feedback to the gate region in response to input AC signal applied to the source or drain region, and whereby the dynamic source-to-drain
resistance to the input signal being substantially independent of said input signal.

23. The transistor of claim 22 wherein said substrate layer is a GaAs semi-insulating substrate layer, said semiconductor layer is a GaAs layer, and said resistive gate region comprises cermet.

24. The transistor of claim 23 wherein said gate region comprises Cr-Si02.

25. A bootstrapped-gate field effect transistor for providing electrically variable resistance comprising:
a semiconductor resistive gate region having a first conductivity type formed on a substrate; and
channel, source, and drain regions formed in a semiconductor layer deposited on the resistive gate region, said semiconductor layer having a second conductivity type,
said gate and channel region forming a semiconductor pn diode,
whereby distributed resistance and
capacitance being presented between the source and drain regions, said distributed resistance and
capacitance providing distributed feedback to the gate region in response to AC input signal applied to said source or drain region, and
whereby the dynamic source-to-drain
resistance to said input AC signal being substantially independent of said AC input signal.

26. The transistor of claim 25 wherein the semiconductor layer is a GaAs layer, and said
substrate layer is a GaAs substrate.

27. The transistor of claim 26 wherein said

GaAs substrate is a semi-insulating GaAs substrate.

28. The transistor of claim 27 wherein said source, drain, gate, and channel regions are implanted GaAs regions.

29. The transistor of claim 25 wherein said source, drain, channel, and gate regions comprise single crystal silicon material.

30. The transistor of claim 29 wherein the substrate is a silicon substrate.

31. The transistor of claim 30 wherein said substrate is a silicon oxide substrate.

32. The transistor of claim 30 wherein said substrate is a sapphire substrate.

33. The transistor of claim 25 wherein said semiconductor layer that includes source, drain, and channel regions forms a mesa on the gate region, exposing the periphery of said gate region.

34. The transistor of claim 25 further comprises source and drain contacts formed on said source and drain regions, respectively.

35. The transistor of claim 34 further comprising a first gate contact formed on the exposed portion of said gate region that is close to said source region, and a second gate contact formed on the exposed portion of said gate region that is close to said drain region.

36. The transistor of claim 25 further comprising:
a first gate contact region formed alongside the drain region, and extending vertically and
outwardly from the gate region, said first gate contact region comprising semiconductor material having a second conductivity type;
a second gate contact region formed
alongside said source region, and extending vertically and outwardly from said gate region, said gate contact region comprising semiconductor material having a second conductivity type;
a first gate contact formed on said first gate contact region; and
a second gate contact formed on said second gate contact region, the transistor being a four-terminal transistor.

37. An electronically variable resistance circuit having input, output and resistance control terminals, for providing an electronically
controllable resistance between the input and output terminals, comprising:
a bootstrapped field effect transistor
("BGFET") having source, drain, and gate terminals;
first capacitive means connected between said gate and source terminals of said BGFET; and
second capacitive means connected between said gate and drain terminals of said BGFET, said source and drain terminals of the BGFET being connected to said input and output terminals of the circuit, respectively, and
said gate terminal of said BGFET being resistively coupled to said resistance control terminal of said circuit.

38. The circuit of claim 37 wherein said BGFET comprising:
channel, source, and drain regions formed in a semiconductor layer deposited on a substrate semiconductor layer,
a resistive gate region comprising resistive material disposed over said channel region,
source and drain contacts formed on the source and drain regions, respectively, for making ohmic contact thereto, and
gate contact deposited on said gate region, said source, drain, and gate contacts being connected to said source, drain, and gate terminals,
whereby said resistive gate region forming with respect to said channel region distributed resistance and capacitance,
said distributed resistance and capacitance providing a distributed feedback to the gate region in response to an input AC signal applied to the source or drain region, and
whereby the dynamic source-to-drain
resistance to said input signal being substantially independent of said input signal;

39. The circuit of claim 38 wherein the gate contact covers substantially the entire gate region.

40. The circuit of claim 38 wherein said substrate layer has substantially higher resistivity than said channel region.

41. The circuit of claim 37 wherein the first capacitive means is a first capacitor.

42. The circuit of claim 37 wherein said second capacitive means is a second capacitor.

43. An electronically variable resistance circuit having input, output and resistance control terminals, for providing an electronically
controllable resistance between the input and output terminals, comprising:
a bootstrapped field effect transistor ("BGFET") having source, drain, first gate, and second gate terminals;
first capacitive means connected between said first gate and source terminals of said BGFET;
second capacitive means connected between said second gate and drain terminals of said BGFET,
said source and drain terminals of the BGFET being connected to said input and output terminals of the circuit, respectively;
first resistive means connected between said first gate terminal and said resistance control terminal; and
second resistive means connected between said second gate terminal and said resistance control terminal.

44. The circuit of claim 37 wherein said BGFET comprising: channel, source, and drain regions formed in a semiconductor layer deposited on a substrate semiconductor layer;
a resistive gate region comprising resistive material disposed over said channel region;
source and drain contacts formed on the source and drain regions, respectively, for making ohmic contact thereto;
a first gate contact formed on a first portion of the gate region that is close to the source region; and
a second gate contact formed on a second portion of the gate region that is close to the drain region,
said source and drain contacts being
connected to said source and drain terminals,
respectively,
whereby said resistive gate region forming with respect to said channel region distributed resistance and capacitance,
said distributed resistance and capacitance providing a distributed feedback to the gate region in response to an input AC signal applied to the source or drain region, and
whereby the dynamic source-to-drain
resistance to said input signal being substantially independent of said input signal;

45. The circuit of claim 44 wherein said substrate layer has substantially higher resistivity than said channel region.

46. The circuit of claim 43 wherein the first capacitive means is a first capacitor.

47. The circuit of claim 43 wherein said second capacitive means is a second capacitor.

48. An electronically variable resistance circuit having first, second and resistance control terminals, for providing an electronically
controllable resistance between the source and drain terminals, comprising:
a bootstrapped-gate field effect transistor comprising:
a semiconductor resistive gate region having a first conductivity type formed on a substrate,
channel, source, and drain regions formed in a semiconductor layer deposited on the resistive gate region, said semiconductor layer having a second conductivity type,
said gate and channel region forming a semiconductor pn diode, and
source, drain, and gate contacting means for contacting the source, drain, and gate regions, respectively,
said source, channel, and drain region forming a signal path, whereby the dynamic source-to-drain resistance being respondent to a control voltage applied to the gate region, and
whereby said resistive gate region forming with respect to said channel region distributed resistance and capacitance,
said distributed resistance and capacitance providing a distributed feedback to the gate region in response to an AC input signal applied to said source or drain region, and
whereby the dynamic source-to-drain
resistance to said input AC signal being substantially independent of said AC input signal;

first capacitive means connected between said gate and source contact means; and
second capacitive means connected between said gate and drain contact means,
said source and drain contacting means being connected to said first and second terminals of the circuit, respectively, and
said gate contact means being resistively coupled to said resistance control terminal of said circuit.

49. The circuit of claim 43 wherein the first capacitive means is a first capacitor.

50. The circuit of claim 44 wherein said second capacitive means is a second capacitor.

51. The circuit of claim 43 wherein the gate contact means comprises a first gate contact connecting a first portion of the gate region that is close to the source region, and a second contact connecting a second portion of the gate region that is close to the drain region, and
said first gate contact being connected to said control terminal via a first resistor, and said first gate contact being coupled to said source contact means through a first capacitor,
said second gate contact being connected to said control terminal via a second resistor, and said second gate contact being coupled to the drain contact means through a second capacitor.

52. An attenuation circuit for providing attenuation between input and output terminals of the circuit, comprising: at least one first bootstrapped-gate field effect transistor ("BGFET") for providing an
electronically variable resistance between its source and drain terminals.

53. The attenuation circuit of claim 47 further comprising second and third field effect transistors.

54. The attenuation circuit of 48 wherein said first, second and third transistors are
configured to form a π-type attenuator circuit wherein said first BGFET is connected between said input and output terminals of said attenuation circuit,
said second FET is connected between the input terminal and the ground potential, and
said third FET is connected between the output terminal and the ground potential.

55. The circuit of claim 49 wherein the second and third FETs are BGFETs.

56. The circuit of claim 48 wherein said three transistor are configured as a T-type
attenuator, wherein said second and third FETs are connected in series between the input and output terminals, and said BGFET is connected between the interception of said second and third FETs and the ground potential.

57. The circuit of claim 51 wherein the second and third FETs are BGFETs.

58. The circuit of claim 47 wherein said BGFET comprising:
channel, source, and drain regions formed in a semiconductor layer deposited on a substrate semiconductor layer,
said substrate semiconductor layer having substantially higher resistivity than said channel region; and
a resistive gate region comprising resistive material disposed over said channel region,
said gate and channel regions forming a junction whereby the source-to-drain resistance being substantially dependent only on said junction, and
whereby said resistive gate region forming with respect to said channel region distributed resistance and capacitance,
said distributed resistance and capacitance providing distributed feedback to the gate region in response to an input AC signal applied to the source or drain region, and
whereby the dynamic source-to-drain
resistance to said input signal being substantially independent of said input signal.

59. The circuit of claim 47 wherein said

BGFET comprising:
channel, source, and drain regions formed in a semiconductor layer deposited on a substrate
semiconductor layer;
a resistive gate region comprising resistive material disposed over said channel region;
source and drain contacts formed on the source and drain regions, respectively, for making ohmic contact thereto; and a gate contact deposited on said gate region, said gate contact covering substantially the entire said gate region,
whereby said resistive gate region forming with respect to said channel region distributed resistance and capacitance,
said distributed resistance and capacitance providing a distributed feedback to the gate region in response to an input AC signal applied to the source or drain region, and
whereby the dynamic source-to-drain
resistance to said input signal being substantially independent of said input signal.

60. A bootstrapped-gate field effect transistor for providing electrically variable resistance comprising:
a semiconductor resistive gate region having a first conductivity type formed on a substrate; and
channel, source, and drain regions formed in a semiconductor layer deposited on the resistive gate region, said semiconductor layer having a second conductivity type,
said gate and channel region forming a semiconductor pn diode,
said source, channel, and drain region forming a signal path, whereby the dynamic source-to-drain resistance being respondent to a control voltage applied to the gate region, and
whereby said resistive gate region forming with respect to said channel region distributed resistance and capacitance,
said distributed resistance and capacitance providing a distributed feedback to the gate region in response to an AC input signal applied to said source or drain region, and
whereby the dynamic source-to-drain
resistance to said input AC signal being substantially independent of said AC input signal.