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1. (WO1993019547) PROCEDE D'AJUSTEMENT DE PHASE ET APPAREIL DESTINE A ETRE UTILISE DANS UN CIRCUIT DE RECUPERATION DU SIGNAL D'HORLOGE
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

1. A method of phase adjustment for a dock recovery scheme, the dock recovery scheme generating a sampling dock signal having a phase and at least a first and a second error signal indicative of the quality of a first received signal, the smaller of the at least first and second error signals is referred to as the minimum error value, each of the at least first and second error signals has a corresponding counter value, the method comprising the steps of:
comparing the at least first and the second error signals to the minimum error value, creating at least a first and a second normalized error magnitude signal corresponding to said comparing;
processing said at least first and second normalized error magnitude signal, and, responsive to said processing, determining a desired phase of the sampling dock signal; shifting, responsive to said desired phase, the phase of the sampling dock signal; and
maintaining, responsive to said desired phase, the phase of the sampling dock signal.

2. A method of phase adjustment in accordance with claim 1 wherein said step of processing further comprises the steps of:
comparing each of said at least first and second
normalized error magnitude signals to a first threshold value; changing, responsive to each of said at least first and said second normalized error magnitude signals being less than said first threshold value, each of the corresponding counter values;
comparing each of said at least first and second
normalized error magnitude signals to a second threshold value;
changing, responsive to each of said at least first and said second normalized error magnitude signals being greater than said second threshold value, each of the corresponding counter values; and
comparing the corresponding counter values to a third threshold value, and, responsive to said comparison, determining a desired phase of the sampling dock signal. 3. A method of phase adjustment in accordance with claim 2 wherein said step of changing, responsive to each of said at least first and said second normalized error magnitude signals being less than said first threshold value, each of the corresponding counter values further comprises a step of incrementing the corresponding counter values.
4. A method of phase adjustment in accordance with claim 2 wherein said step of changing, responsive to each of said at least first and said second normalized error magnitude signals being greater than said second threshold value, each corresponding counter values further comprises the step of decrementing the corresponding counter values.
5. A method of phase adjustment in accordance with claim 1 wherein the at least first and second error signals represent sampling the received signal at at least a first and a second phase, consequently said step of shifting the phase of the sampling dock further comprises shifting to the phase corresponding to the counter value which reaches said third threshold, and step of maintaining the phase of the sampling dock further comprises maintaining the current phase of the sampling dock signal if none of the counter values reach said third threshold.

6. A phase adjustment apparatus for use in a clock recovery circuit, the dock recovery circuit generates a sampling clock signal having a phase and at least a first and a second error signal indicative of the quality of a first received signal, the smaller of the at least first and second error signals is referred to as the minimum error value, each of the at least first and second error signals has a corresponding counter value, the phase adjustment apparatus comprising:
means for comparing the at least first and the second error signals to the minimum error value, creating at least a first and a second normalized error magnitude signal
corresponding to said comparing;
means for processing said at least first and second normalized error magnitude signals, and, responsive to said processing, determining a desired phase of the sampling dock signal;
means for shifting, responsive to said desired phase, the phase of the sampling dock signal; and
means for maintaining, responsive to said desired phase, the phase of the sampling dock signal.

7. A phase adjustment apparatus in accordance with claim 6 wherein said means for processing further comprises: means for comparing each of said at least first and second normalized error magnitude signals to a first threshold value; means for changing, responsive to each of said at least first and said second normalized error magnitude signals being less than said first threshold value, each of the
corresponding counter values;
means for comparing each of said at least first and second error magnitude signals to a second threshold value;
means for changing, responsive to each of said at least first and said second normalized error magnitude signals being greater than said second threshold value, each of the corresponding counter values; and
means for comparing the corresponding counter values to a third threshold value, and, responsive to said comparison, determining a desired phase of the sampling dock signal.

8. A phase adjustment apparatus in accordance with claim 7 wherein said means for changing, responsive to each of said at least first and said second normalized error magnitude signals being less than said first threshold value, each of the corresponding counter values further comprises means for incrementing the corresponding counter values. 9. A phase adjustment apparatus in accordance with claim 7 wherein said means for changing, responsive to each of said at least first and said second normalized error magnitude signals being greater than said second threshold value, each corresponding counter values further comprises means for decrementing the corresponding counter values.

10. A radiotelephone including a dock recovery circuit for providing an output dock signal which is synchronized with a received data signal when the radio transceiver is receiving , and which maintains continuous bit synchronization for a given period of time when the data signal is not received, the radiotelephone comprising:
means for receiving an RF signal having a data signal modulated thereon, and for demodulating said received RF signal to provide a received data signal; and
the dock recovery circuit comprising:
means for generating at least a first and a second error signal;
means for comparing the at least first and the second error signals to the minimum error value, creating at least a first and a second normalized error magnitude signal corresponding to said means for comparing;
means for processing said at least first and second normalized error magnitude signal, and, responsive to said processing, determining a desired phase of the output dock signal;
means for shifting, responsive to said desired phase, the phase of the output dock signal; and
means for maintaining, responsive to said desired phase, the phase of the sampling dock signal.