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1. (WO1990006633) MODULES DE DONNEES HF MICROCOMMANDES
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CLAIMS

What is claimed is:

1. A communication system, comprising:
at least one base station and at least one remote module, each comprising at least one RF transmitter and at least one RF receiver, and each connected to mutuaUy communicate using a pulse code modulation protocol;
wherein said remote module is battery-powered, and comprises an antenna,
a serial data bus internal to said portable module,
plural integrated circuits, mutuaUy connected through said serial data bus and which are connected and programmed to receive and decode RF signals from said base station, and
memory which is read/write accessible over said serial data bus.

2. A micropowered wireless data module, comprising:
a power source;
a serial data bus internal to said portable module;
plural integrated circuits mutuaUy connected through said serial data bus, ones of said integrated circuits being connected and programmed to receive and decode RF signals, said plural integrated circuits including memory which is read/write accessible over said serial data bus, and
access control drcuitry, connected to provide password protection for access to said memory with respect to a user-changeable password;
a sending interface, which is connected to perform wireless data transmission in accordance with signals on said serial data bus;
a receiving interface, which is connected to receive wireless data transmissions and to control said serial data bus and to drive command and data signals on said serial data bus accordingly;
wherein said receiving interface unit provides translation from a duration-modulated code to the data format of said serial data bus.

3. A low-power RF receiver, comprising:
a battery;
at least one antenna circuit, tuned to at least one predetermined reception frequency;
at least one comparator, having a pah of inputs directly connected to receive a low-level analog signal at said predetermined frequency from said antenna circuit;
at least one digital logic stage, connected to be driven by the output of said comparator and provide a fuU digital output corresponding to the voltage received at said comparator ;
said comparator and said logic stage being connected to be powered by said battery.

4. A wireless data module, comprising:
an RF receiver and antenna, capable of RF reception at a first frequency;
an RF transmitter and antenna, capable of RF transmission at a second frequency which is different from said first frequency;
a memory connected to selectably store data received through said receiver, and to selectably read data for transmission by said transmitter, to provide two-way data communication using said first and second frequencies; and
conductive signal contacts, connected to said transmitter and receiver in such relation that said memory can also selectably store data received through said contacts in an RF signal, and can selectably read data for RF transmission through said contacts, to provide two-way data communication through said contacts, using substantiaUy the same protocols as are used in said wireless data communication.

5. A multiport memory system, comprising:
a plurality of multiport memory controUer ' chips, each comprising
a paraUel port interface;
a paraUel memory interface, separate from said paraUel port; and
a serial port interface, comprising circuits connected and programmed to receive bit streams in a predetermined serial format, including a predetermined protocol for overhead bits, and to provide corresponding outputs to said memory interface in a paraUel output;
one or more integrated circuit memories, connected to said paraUel memory interface of one of said controUer chips;
wherein said memory interface of at least one of said controUer chips is directly connected to said paraUel port interface of another of said controUer chips;

whereby said respective serial ports of multiple ones of said controUer chips share multiport access to said memory interface of one of said controUer chips.

6. A method for data communication, in a system which includes one or more base stations each including a wireless transmitter and receiver, and one or more remote modules each including a wireless transmitter and receiver, comprising the steps of:
a) from one of said base stations: broadcasting a query signal; b) in one of said micropowered portable modules which is within range of said query signal: receiving said query signal, and transmitting a beacon in response thereto;
c) in said base station: receiving said beacon, and transmitting a command to said module to read out data, and thereafter transmitting a series of read-data symbols;
d) in said module: transmitting, in synchrony with said series of read-data symbols, a series of signals which each indicate the value of one bit of data;
e) in said base station, if a write transaction is desired: transmitting a command to said module to write in data, and thereafter transmitting a series of write-data symbols of first and second types;
f) in said module, if a write transaction is desired: receiving and decoding said series of write-data symbols, to define a sequence of bits, and storing said sequence of bits;
wherein said read-data symbol is substantiaUy the same as one of said write-data symbols.

7. A portable wireless-accessible data module, comprising:
receiver circuits capable of receiving electromagnetic radiation at a first frequency;
a transmitter capable of transmitting electromagnetic radiation at a second frequency, and
coding and data handling circuits connected so that the module can carry on data communications at low RF power levels, on said first and second frequendes, with another station while in proximity thereto; wherein said receiver circuits comprise
a first amplifier
which has a bandwidth wide enough to track signals at said first frequency and
which is connected to receive signals at said first frequency, and
a second amplifier
which is connected to receive signals at a third frequency which is much lower than said first frequency, and
which has a bandwidth which is not wide enough to track signals at said first frequency, but is high enough to track signals at said third frequency;
and wherein said remote module, when not sending or receiving data, monitors said third frequency substantiaUy continuously, but does not monitor said first frequency continuously;
and wherein said remote module, when not monitoring said first frequency, does not begin to monitor said first frequency untfl a predetermined coded command is received on said third frequency.

8. A wireless communication system, comprising:
at least one base station, and multiple remote modules, each comprising at least one RF transmitter and at least one RF receiver;
wherein said base station comprises
a first transmitter capable of operation at a first frequency, and
a second receiver capable of operation at a second frequency
and wherein said remote module comprises
a first receiver capable of operation at said first frequency, and
a second transmitter capable of operation at said first frequency;
and said transmitters and receivers are connected so that said base station and said remote module can cany on data communications on said first and second frequendes, but only while in mutual proximity;
wherein said base station can broadcast a polling command to ascertain what remote modules are in proximity at a given moment;
and wherein ones of said modules, if in proximity to said base station, respond to said polling command with a response which includes an identification field;
and wherein at least a subfield of said identification - contains bit positions which are individuaUy, and not combinatoriaUy or numericaUy, assigned to correspond to respective subclasses of said remote modules;
and wherein said base station contains logic to decode responses to said polling command, and to determine the presence of multiple ones of said subclasses of said modules, if ones of said subclasses simultaneously respond to said polling command.

9. A communications receiver, comprising:
front end circuits, which receive wireless incoming signals and provide, as corresponding digital outputs, variable-length bursts of constant-width pulses;
counter logic, which counts the pulses in said bursts, and recognizes the end of a burst when a predetermined minimum silence period occurs;
thresholding logic, which compares values accumulated by said counter logic against a set of multiple boundary values, to provide a set of signals indicating the results of said comparisons;
a state machine, which translates said set of signals into output signals to selectively drive appropriate output lines in accordance with the encoded signal received.

10. A wireless-accessible portable data module, comprising:
a battery;
communication interface drcuits, powered by said battery, including
an RF receiver capable of operation at a first frequency, and
an RF transmitter capable of operation at a second frequency;
a data access pathway comprising
coding logic, and
at least 214 bits of solid-state memory;
a data connector; and
a multiport memory controUer which arbitrates access to said memory between said data connector and said interface drcuits;
said module also being connected to receive a power supply input through said data connector;
whereby, when a connection is made to said paraUel port of a respective remote module;, data can be rapidly downloaded from said memory without burdening said battery.

11. An integrated bandpass filter drcuit, for-providing a passband with predetermined upper and lower passband edge frequencies, comprising: a first digital circuit which has an input and an output, said output responding with low-pass frequency-domain response characteristics, which include a sharp cutoff at approximately the lower passband edge frequency, to signals apphed at the input thereof;
a second digital drcuit which has an input and an output, said output responding with low-pass frequency-domain response characteristics, which include a sharp cutoff at approximately the upper passband edge frequency, to signals apphed at the input thereof;
a thhd digital circuit which implements a counter function, and which comprises input connections including at least
a first input having functionality analogous to a conventional counter's reset input, and
a second input having functionality analogous to a conventional counter's clock input;
wherein the output of said first digital circuit is connected to drive said first input of said thhd drcuit, and the output of said second digital circuit is connected to drive said second input of said thhd circuit; whereby the output of said thhd digital circuit provides said bandpass filter function.

12. An integrated drcuit, comprising:
a connection for receiving a primary power supply input;
a connection for receiving a secondary power supply input;
a connection for receiving a ground voltage;
a connection for providing a power supply output, and drcuitry which is configured to connect said power supply output to whichever of said power supply inputs is more different from said ground voltage;
connections for a reset line, a clock line, and at least one data line of a serial bus, and drcuitry which is configured to provide outgoing data transfer over said serial bus;
a connection for providing a reference voltage output, and chcuitry which is configured to switch said reference voltage output so that when said reset line connection is driven to a first state thereof, said reference voltage output is driven to a respective first state thereof;
and when said reset line connection is driven to a second state thereof, said reference voltage output is driven to a respective second state thereof;
wherein said second state of said reset line connection has a greater voltage to ground than does said first state of said reset line connection,
and wherein said second state of said reference voltage output has a smaUer voltage to ground than does said first state of said reference voltage output

13. A wheless data module, comprising:
a battery;
memory;
a memory controUer chip, including
a paraUel port interface;
a memory interface, separate from said paraUel port; and
a serial port interface, comprising drcuits connected and programmed to receive bit streams in a predetermined serial format, including a predetermined protocol for overhead bits, and to provide corresponding outputs to said memory interface in a paraUel output;
an arbitration register which is accessible in a memory address space which is common to memory accessible through said memory interface, and which contains arbitration bits indicating which port is performing memory access through said memory interface, some of said arbitration bits being read-accessible through said serial port, but write-accessible only through said paraUel port, and others of said arbitration bits being read-accessible through said paraUel port, but write-accessible only through said serial port;
wherein said serial access protocol normaUy requires separate access cycles for read accesses and for write accesses to memory space, but also includes a special command which permits said serial port to sequentiaUy read, write, and read ones of said arbitration bits within a single access cycle;
a complex integrated circuit, having a paraUel port interface which is connected to said paraUel port interface of said controUer chip; wheless interface chcuitry, comprising elements connected to receive and to transmit wheless signals, and having a serial data interface which is connected to said serial port interface of said controUer chip.

14. An integrated circuit, comprising:
input contacts connectable to an antenna;
a battery terminal, for connection to a battery;
enable logic, connected to said input contacts, comprising insulated gate field effect transistors which are connected to turn on only when the antenna provides a voltage greater than the threshold voltage of said transistors; and
other drcuits which have significant standby power consumption requirements and which are selectably connected to said battery terminal; wherein said enable logic is connected to selectively disable said other drcuits, and does not permit said other chcuits to operate until said enable logic has detected a strong electromagneticaUy radiated signal at a predetermined low frequency.

15. The system of Claim 1, wherein said remote module comprises at least one integrated circuit memory.

16. The system of Claim 1, wherein said remote module comprises at least one integrated drcuit which implements access control restrictions.

17. The system of Claim 1, wherein the total set of symbols transmitted by said base station includes
a first symbol which encodes a write command for a first data bit state, and which also, during read mode, provides tuning for reading one bit of data;
a second symbol which encodes a write command for a second data bit state;
a thhd symbol which encodes a reset command; and
a fourth symbol which encodes a command to turn on a wheless beacon;
wherein said first, second, thhd, and fourth symbols each have respectively different durations;

and wherein said first and second symbols each have a duration less than that of either of said thhd and fourth symbols.

18. The system of Claim 1, wherein said remote module is hand- portable.

19. The system of Claim 8, wherein at least some ones of said bits of said subfield are specificaUy assigned to individual ones of said remote modules.

20. The system of Claim 8, wherein some number N of said bit positions of said identification are combinatoriaUy assigned to 2N of said remote modules, and N is greater than two.

21. The system of Claim 1, wherein at least one of said remote modules comprises an access control chip, which is connected to said serial data bus and which is connected to provide password protection for said memory.

22. The system of Claim 1, wherein at least one of said remote modules comprises a microprocessor.

23. The method of Claim 6, wherein said beacon is chopped at a predetermined frequency.

24. The method of Claim 6, wherein each transaction of said steps a) b) c) and d) includes only a predetermined fixed total number of symbols.

25. The method of Claim 6, further comprising the additional steps, after said step c) and before said step e), of
g) in said base station: transmitting a chip-select signal;

h) in said module: comparing said chip-select signal with an internahy stored value;
i) in said module: transmitting an identification signal, if said chip-select signal matches said inteπiaUy stored value;
j) in said base station: transmitting a password; and
k) in said module: comparing said password with an internaUy stored value.

26. The method of Claim 6, further comprising the additional steps, after said step c) and before said step e), of
g) in said base station: transmitting a chip-select signal;
h) in said module: comparing said chip-select signal with an internaUy stored value;
i) in said module: transmitting an identification signal, if said chip-select signal matches said internaUy stored value;
j) in said base station: transmitting a password; and
k) in said module: comparing said password with an internaUy stored value, and generating false data if said password does not match said internaUy stored value.

27. The method of Claim 6, wherein the total set of symbols transmitted by said base station includes
a first symbol which encodes a write command for a first data bit state, and which also, during read mode, provides timing for reading one bit of data;
a second symbol which encodes a write command for a second data bit state;
a thhd symbol which encodes a reset command; and
a fourth symbol which encodes a command to turn on a wheless beacon;
wherein said first, second, thhd, and fourth symbols each have respectively different durations, and wherein said first and second symbols each have a duration less than that of either of said thhd and fourth symbols.

28. The method of Claim 9, wherein, during said step b), said base station scans a narrow-band band pass filter across a range of frequendes in which said beacon is expected to faU.

29. The method of Claim 9, wherein the range of said query signal is approximately 5 feet or less.

30. The module of Claim 2, further comprising an access control chip, which is connected to said serial data bus and which is connected to provide password protection for said memory.

31. The module of Claim 4, further comprising an access control chip, which is connected to said serial data bus and which is connected to provide password protection for said memory.

32. The module of Claim 2, wherein said remote module further comprises a microprocessor, which is connected to have access to said memory over said serial data bus.

33. The module of Claim 2, wherein said remote module weighs less than 10 ounces and has a total volume of less than 10 cubic inches.

34. The module of Qaim 2, further comprising a memory controUer chip, which is connected to provide an interface between an array of memory cells and said serial data bus.

35. The module of Claim 7, wherein said data access pathway can receive data through said contacts at a frequency which is different from said first frequency and which falls in a frequency range of about one- thhd of said first frequency to three times said first frequency, and wherein said data access pathway can send data through said contacts using a carrier frequency which is different from said first frequency and which fa .ls in a frequency range of about one-thhd of said second frequency to three times said second frequency.

36. The module of Qaim 7, wherein said data access pathway can receive data through said contacts at a thhd frequency which is different from said first frequency, and wherein said data access pathway can send data through said contacts using, as a carrier frequency, a fourth frequency which is different from said second frequency.

37. The module of Claim 4, wherein said first and second frequendes are much less than 100 GHz.

38. The module of Qaim 4, wherein said first frequency is less than 1 MHz, and said second frequency is greater than 30 MHz.

39. The module of Qaim 13, wherein said check value provided by said error-checking logic is also tested at the end of data transfers.

40. The module of Claim 13, wherein said error-checking logic is included in said memory controUer.

41. The module of Claim 13, wherein said memory controUer contains a protocol register which stores incoming commands while said check value is being tested.

42. The module of Qaim 13, wherein said wheless interface chcuitry is configured to receive infrared signals.

43. The module of Claim 13, wherein said wheless interface chcuitry is configured to receive ultrasonic signals.

44. The module of Qaim 10, wherein said battery is non-rechargeable.

45. The receiver of Claim 3, wherein said fuU digital output is at the same frequency as said low-level analog signal.

i 46. The receiver of Qaim 3, wherein said low-level analog signal has a frequency below 10 MHz.

47. The receiver of Claim 3, wherein said low-level analog signal has a frequency below 1 MHz.

48. The receiver of Qaim 3, wherein said comparator receives a standby current which is regulated by a current source, and wherein said current source comprises multiple current-source devices in paraUel, and switching transistors which are connected in series with individual ones of said current-source devices, to enable or disable ones of said current- source devices; and further comprising current-source-control logic, connected to control said switching transistors, and thereby enable or disable ones of said current-source devices, in accordance with signal detection characteristics seen at a later stage.

49. The receiver of Claim 3, wherein said comparator receives a standby current which is regulated by a current source, and wherein said current source comprises multiple current-source devices in paraUel, and switching transistors which are connected in series with individual ones of said current-source devices, to enable or disable ones of said current- source devices; and further comprising current-source-control logic, connected to control said switching transistors, and thereby enable or disable ones of said current-source devices, in accordance with signal detection characteristics seen at a later stage; and wherein the widest of said current-source devices is at least four times as wide as the narrowest of said current-source devices.

50. The receiver of Qaim 3, comprising at least two of said antenna chcuits, both tuned to a predetermined reception frequency; and at least two of said comparators, each having a respective pah of inputs directly connected to receive a low-level analog signal at said predetermined frequency from a respective one of said antenna chcuits.

51. The integrated drcuit of Qaim 11, wherein said thhd digital circuit is a counter.

52. The integrated drcuit of Claim 11, wherein said first logic gate is an inverter.

53. The integrated circuit of Qaim 11, wherein said first logic gate is a NAND gate. - . .

54. The integrated circuit of Qaim 11, wherein said first and second digital drcuits are inverters, and wherein said first digital drcuit comprises a resistor connected in series with the output of said first digital drcuit

55. The integrated drcuit of Qaim 12, further comprising a connection for an additional serial data input, separate from said serial bus.

56. The integrated drcuit of Qaim 12, further comprising a connection for keying a wheless transmitter.

57. The integrated drcuit of Qaim 14, wherein said other chcuits include wheless interface drcuits.

58. The integrated drcuit of Qaim 14, wherein said enable logic does not permit said other drcuits to operate until said enable logic has detected a strong electromagneticaUy radiated signal with a predetermined coded pattern at said predetermined low frequency.

59. The integrated drcuit of Qaim 14, wherein said enable logic can also command said other drcuits to cease operation if enable logic has detected a strong electromagneticaUy radiated signal with a predetermined coded pattern at said predetermined low frequency.

60. The integrated circuit of Claim 14, wherein the output of said enable logic is connected to change the state of at least one bit of nonvolatile memory, and said nonvolatile memory bit controls logic gates in said other chcuits.

61. The integrated circuit of Qaim 14, further comprising a filter drcuit which blocks the output of said enable logic unless energy near said predetermined low frequency is much stronger than energy at other frequendes.

62. The integrated drcuit of Claim 14, wherein said predetermined low frequency is below 3000 Hz.