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1. (WO1990006626) AMPLIFICATEUR A ENTREE SIMPLE ET A SORTIE DIFFERENTIELLE
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

Claims
We claim as our invention:

1. A single input, differential output amplifier having reduced phase error, comprising:
an inverting stage for driving an independent load , including an input port, an output port , and an inverting
transistor,
a non-inverting stage for driving another
independent load Λ including an input port, an output port, and a non-inverting transistor ,
said input port of said inverting stage being coupled to said input port of said non-inverting stage for simultaneously receiving an input signal.

2. A single input, differential output amplifier as defined in claim 1 , in which said inverting transistor comprises an inverting FET and said non-inverting transistor comprises a non-inverting FET.

3. A single input, differential output amplifier, comprising:
an inverting stage having an input port, an output port, and an inverting transistor,
a non-inverting stage having an input port, an output port, and a non-inverting transistor, said input port of said inverting stage being coupled to said input port of said non-inverting stage for simultaneously receiving an input signal, said inverting stage and said non-inverting stage each include a FET, said FET of said non-inverting stage being arranged in a common gate configuration..

4. A single input, differential output amplifier, comprising:
an inverting stage having an input port and an output port,
a non-inverting stage having an input port and an output port, said input port of said inverting stage being coupled to said input port of said non-inverting stage for simultaneously receiving an input signal,
said inverting stage and said non-inverting stage each includes a FET, said FET of said inverting stage being arranged in a common source configuration.

5. A single input, differential output amplifier,
comprising:
an inverting stage having an input port and an output port,
a non-inverting stage having an input port and an output port, said input port of said inverting stage being coupled to said input port of said non-inverting stage for simultaneously receiving an input signal,
said inverting stage and said non-inverting stage each includes a FET, said FET of said non-inverting stage being arranged in a common gate configuration, and said FET of said inverting stage being arranged in a common source configuration.

6.- In a single input, differential output amplifier, driving independent loads, a method for reducing phase error
comprising the steps of:
(a) providing a non-inverting stage having an input port, an output port, and a non-inverting transistor,
(b) providing an inverting stage having an input port , an output port, and an inverting transistor,
(c) coupling said input port of said non-inverting stage to said input port of said inverting port.

7: Method of reducing phase error of claim 6, in which step (a) comprises providing an inverting field effect transistor, and step (b) comprises providing a non-inverting field effect transistor.

8. Method of reducing phase error comprising:
(a) providing a common gate field effect transistor non-inverting stage having an input port and an output port,
(b) providing a common source field effect
transistor inverting stage having an input port and an output port,
(c) coupling said input port of said non-inverting stage to said input port of said inverting stage.