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The present invention relates to signal processing.

According to the invention, there is provided an asynchronous amplitude to discrete signal converter, comprising means for converting the amplitude of an input signal into a discrete value signal, means for producing a latch signal in response to a change in value of the discrete value signal, and means for latching the discrete value signal in response to the latch signal.

Preferably the means for producing the latch signal is arranged to produce the latch signal after a
predetermined delay following a change in value of the discrete value signal.

The converting means may comprise a plurality of comparators having first inputs for receiving the input signal and second inputs arranged to receive respective reference voltages.

A priority encoder may be connected to the output of the latching means.

The converter may be used as an analog-digital converter, in which case the output signal from the priority encoder may be a binary or binary-coded-decimal representation of the amplitude of the input signal.

The converter may also be used as an amplitude division demultiplexer, in whi-eh case the priority encoder provides separate signals corresponding to separate input signals which were amplitude division multiplexed to provide the input signal to the converter.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which:

Figure 1 shows graphs against time of examples of signals to be converted to digital signals;

Figure 2 is a block circuit diagram of an amplitude to discrete signal converter constituting a preferred embodiment of the invention; and

Figure 3 shows graphs against time of input and output signals illustrating operation of the converter of Figure 2.

A known type of converter for converting or decoding from the analog or amplitude domain into some other representation such as the digital domain is based on periodic sampling of the input signal. Such a converter is adequate in many applications but is usable only for relatively limited bandwidth signals. Various problems arise when attempting to use such a converter for relatively wide bandwidth signals. Thus, the sampling frequency, which must be at least twice the highest frequency component of the signal, has to be
correspondingly high in order to sample wide bandwidth signals. Also, the bandwidth for transmission of the digital representation in, for instance, a pulse code modulation system increases with the sampling frequency and also with the number of bits required to represent the sampled values of the input signal.

Even when such converters are capable of handling a relatively smoothly changing input signal, for instance of the type shown at graph (a) of Figure 1 by f (t), such converters are not generally suitable for use with a stepped waveform for instance of the type shown in graph (b) of Figure 1 by f (t). Such waveforms can occur in composite video signals, for instance of the type used to display text or graphics on a cathode ray tube display where each scanned line is divided into segments corresponding to picture elements (pixels). In such an application, it is necessary to sample the input signal at exactly the same place for every displayed frame as otherwise the display will provide an optical illusion of noise wandering through the displayed image. If the sampling rate is increased in order to try to overcome this problem, this may lead to sampling rates and data transmission rates which are unacceptably or unachievably high. Also, the sampling clock
frequency may not be related to the basic clock
frequency of the display, in which case there will be a relative drift in the sampling precision with time.

Figure 2 shows a converter constituting a preferred embodiment of the present invention and illustrates its application to analog-digital conversion. However, the converter may equally well be used for amplitude
division demultiplexing.

The converter comprises a plurality of comparators

150 , .... 150 whose non-inverting inputs are
connected together and to an input 151 for receiving an input signal f(t) to be converted. The inverting inputs of the comparators 150Λ O, .... 150n are connected to receive respective reference voltages supplied by a potential divider comprising resistors 151, 152 , ...,

152n, a constant current source 153, and a constant voltage source 154. The outputs of the comparators 150OΛ, .... 150n are connected to the inputs Do ,
..., D of a data latch 155.

The outputs of the comparators 150 , .... 150 are connected to first inputs of EXCLUSIVE-OR gates

156 , .... 56 and to the inputs of inverter-delay circuits 157ΛO, .... 157n . The inverter-delay
circuits are arranged to supply at their outputs an inverted and delayed version of the input signal. The outputs of the circuits 157 , .... 157 are
connected to the second inputs of the gates 156 , ..., 156 , respectively. The outputs of the gates 156 , ... , 156 are connected to respective inputs of a NAND gate 158, whose output is connected to the clock input of the latch 155.

The outputs , ..., Q of the latch 155 are connected to respective inputs N0o, .... Nn of a
priority encoder 159. In the embodiment shown, the priority encoder is arranged to form the logarithm to the base 2 of the number represented by the parallel data on its inputs, so that the outputs BΛu, .... B„n of the encoder provide a binary representation of the input signal f (t) .

When an input signal of constant amplitude, or of an amplitude which varies between limit values such that none of the comparators 150 , .... 150 changes
state, is received, the first and second inputs of each of the gates 156 , .... 156 are at different logic levels so that the output of each gate is at logic level 1. All the inputs to the gate 158 are therefore at logic level 1 and the output of the gate 158 is at logic level 0. The latch 155 is therefore prevented from latching new data and maintains on its" outputs the previously latched data. This is encoded by the encoder 159 to a binary representation and forms the output of the converter.

When the input signal varies sufficiently for at least one of the comparators to change the state of its output, for instance the comparator 150 , the signal level at the first input of the gate 156 will change but that at the second input will not change immediately because of the effect of the circuit 157 . For a period equal to the delay period provided by the circuit 157 , both inputs of the gate 156 will be at the same logic level and hence for the same period the output of the gate 156 will be at 0 logic level. The output of the gate 158 will therefore be at logic level 1 for this same period, thus latching the data
corresponding to the new signal level into the latch 155. This new data is encoded by the encoder 159 and supplied at its outputs. If more than one comparator changes the state of its output, the latch 155 will remain open until the end of the predetermined time delay after the last-to-change comparator has changed its output state.

The converter therefore functions asynchronously and performs sampling in response to changes in the input signal. The effective sampling frequency therefore varies with the signal and is, at any time, of a
sufficiently high value to encode properly the input signal. The digital output signals are transmitted at a rate which is sufficient to represent the input signal. Minimum bandwidth requirements are therefore placed on the converter circuitry and on the transmission path to which the converter is connected.

Figure 3 illustrates operation of a converter of the type shown in Figure 2 for performing three bit
analog-digital conversion of a stepped waveform, for instance for controlling a raster-scanned video
display. The input signal f(t) is capable of assuming any one of a plurality of values or "images" f , .... f with substantially instantaneous transition between consecutive values. The binary outputs representing 2 0, 21 and 22 are shown against the same time
axis. Whenever the value of the input signal changes, the input signal is effectively resampled and the new binary representation appears after the short delay (too short to be visible in the graph of Figure 3) at the digital output. However, when the value of the input signal remains substantially constant, no sampling takes place and the previously sampled value remains latched.

The use of such a converted therefore minimises bandwidth requirement and is also capable of being used in a visual display system of the type in which
horizontal segments of raster-scanned lines represent pixels. For instance, in this type of display in which each pixel is controlled by a binary value, the
converter is effectively synchronised to the start of each pixel so that no illusion of noise or relative drift takes place.

The converter may also be used for amplitude
division de-multiplexing, which may necessitate using a different type of priority encoder 159 and altering the voltage reference values supplied to the second inputs of the comparators 150 OΛ. .... 150n. In the case
where binary signals have been amplitude division multiplexed to provide the input signal f(t) to the converter, the voltage references and encoder may be as shown in Figure 2 and each of the parallel output lines of the encoder then supplies the demultiplexed binary signal.

For relatively slowly varying input signals, the circuits 157 , ..., 157 may comprise an inverter followed or preceded by a RC integrating network in order to provide a suitable delay. However, for input signals whose amplitudes vary more quickly and for elements capable of operating at relatively high speed, the propagation delay of an inverter may be sufficient to provide a suitable delay without the use of an integrating circuit or other means. The total delay between a change of state of the output of one of the comparators and completion of latching into the latch 155 ensures that the new state of the comparator outputs is latched into the latch. When the input signal is changing so rapidly that the period between consecutive comparator output state changes is less than the
predetermined time delay, the latch 155 is held open so that the priority encoder follows the variation in the input signal. However, if the encoder is not capable of following such rapidly changing inputs, further means may be provided, for instance, to hold constant the input to the encoder until the input signal has stopped changing value. This may be applicable, for instance, to an input signal of the type shown in Figure 3 which steps between discrete values.


(51) International Patent Classification 4 (11) International Publication Number : WO 88/ 03 H03 M 1/36 A3 (43) International Publication Date: 19 May 1988 (19.05

(21) International Application Number: PCT/GB87/00791 (74) Agent: ROBINSON, John, Stuart; Marks & Cl
57-60 Lincoln's Inn Fields, London WC2A 3LS (G

(22) International Filing Date: 9 November 1987 (09.11.87)
(81) Designated States: AT (European patent), BE (E

(31) Priority Application Number: 8626655 pean patent), CH (European patent), DE (Europ
patent), FR (European patent), GB (European

(32) Priority Date: 7 November 1986 (07.11.86) tent), IT (European patent), JP, LU (European
tent), NL (European patent), SE (European pate

(33) Priority Country : GB US.

(71) Applicant (for all designated States except US): EMCO Published
DISPLAY TECHNOLOGY LIMITED [GB/GB]; 158 With international search report.
Camberwell Road, London SE5 OEE (GB). Before the expiration of the time limit for amending t
claims and to be republished in the event of the receipt

(72) Inventors; and amendments.
(75) Inventors/Applicants (for US only) .-CURTIS, Clive, Ronald [GB/GB]; 28 Slades Garden, Enfϊeld, Middlesex (88) Date of publication of the international search report: (GB). WAKEMAN, Clifford, John [GB/GB]; 5 16 June 1988 (16.06 Strangford Road, Tankerton, Whistable, Kent CT5
2EP (GB).


(57) Abstract
An asynchronous amplitude to discrete signal converter comprises a plurality of comparators (150o-150n) whi compare an input signal (f(t)) with respective reference voltages and supply a discrete value signal to a latch (155). A lat signal is produced by an arrangement (1560-156n, 1570-157n, 158) after a short delay following any change in the discr value signal. A priority encoder (159) converts the discrete value signal as required, for instance so that the converter p forms analog-digital conversion or amplitude demultiplexing.


Codes used to identify States party to the PCT on thefrontpages of pamphlets publishing international applications under the PCT.
AT Austria FR France ML Mali
AU Australia GA Gabon MR Mauritania
BB Barbados GB United Kingdom MW Malawi
BE Belgium HIT Hungary NL Netherlands
BG Bulgaria IT Italy NO Norway
BJ Benin SP Japan RO Romania
BR Brazil KP Democratic People's Republic SD Sudan
CF Central African Republic ofKorea SE Sweden
CG Congo KR Republic of orea SN Senegal
CH Switzerland LI Liechtenstein. SU Soviet Union
CM Cameroon LK Sri Lanka TD Chad
DE Germany, Federal Republic of LU Luxembourg TG Togo
DK Denmark MC Monaco US United States of America
FI Finland MG Madagascar