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1. (WO1980001528) CIRCUIT LOGIQUE TAMPON A TROIS ETATS
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TRI-STATE LOGIC BUFFER CIRCUIT

Field of the Invention
This invention relates to semiconductor apparatus and more particularly to semiconductor logic circuits characterized by three voltage states.
Background of the Invention
As known in the art, in many logic circuit applications, including those which are not controlled by a master timing clock ("asychronous"), it is desirable to operate with three-state ("tri-state") capability. More specifically, it is desirable to have a number of separate buffer circuits each connecting a different one of a number of separate binary digital local input signal sources to a common data bus line. Each such buffer circuit has an output terminal connected to said common bus line, in order to deliver the corresponding digital local input signal to this common bus line if, and only if, no other signal is then actively present on that line from other sources;
and otherwise to float (i.e., to present a very high impedance to the common data bus line).
For purpose of illustrating these concepts and with reference to FIG. 1, a binary digital "1" or "0" signal ("high" or "low" voltage) may or may not actively be present from other sources (not shown) on a common data bus line 11 at a given moment. By a signal "actively" present from other sources on the common data bus line is meant a low impedance driven signal from another source. In the absence of any such active signal from other sources, the common data bus line 11 is electrically "floating"; that is to say, it has a very high impedance to ground. Only if this common data bus line 11 is "floating" can a buffer circuit 20 be enabled by a control signal from the
source 13 to allow passage of a local binary digital input signal 14 to an output terminal 12 on the bus line 11.
If there is a signal already actively present on the common data bus line 11, then the control signal source 13 prevents the buffer circuit 20 from passing any local signal 14 to the common data bus line 11. This causes the buffer circuit to present a very high impedance to the bus line; that is, the output of the buffer circuit 20 at terminal 12 is electrically in the "floating" state.
Terminal 12 thus serves as a local signal output terminal of the buffer circuit 20. Since the local input signal 14 itself can be a "high" voltage (digital "1") or a "low" voltage (digital "0"), there are three possible
local outputs or "states" ("1", "0", "float") of the buffer circuit 20 at its output terminal 12, depending upon the states of both the local signal input 14 and the control signal delivered by the source 13, all in accordance with the following:
Local Control Non-Inverting
Signal Signal Buffer Circuit
14 13 Output
0 1 float
1 1 float
0 0 0
1 0 1

In the prior art, such a tri-state buffer circuit has been proposed in the form of an MOS integrated circuit, in N-MOS technology for example (FIG. 2). Basically such a circuit includes a pair of MOS NOR-gates (formed by
transistors Q3, Q4, 4; Q5, Q6, ) feeding an MOS output



load device including an output "driver" transistor Q2 and an output load transistor Q1. It should be understood that each of the transistors Q4 and Q6 is a high
transconductance transistor serving as a driver and is substantially identical to its corresponding parallel connected twin transistor
and
, respectively. The transistors Q3 and Q5 are relatively low transconductance transistors serving as load elements. The gate electrode of each of the transistors Q3 and Q5 is connected to the drain terminal of the respective transistor when using such enhancement mode N-MOS devices.
All transistors in the circuit shown in
FIG. 2 are enhancement mode transistors, with the same threshold of typically about 1.2 volts. However, such a circuit requires both a relatively high, voltage supply (VGG = +12 volts) in addition to a relatively low
voltage supply (VDD = +5 volts) for reliable operation, because the inherent threshold voltage of the output load transistor Q1 produces a "back-gate bias" of Q1
itself when it is in the "on" condition. This "back-gate bias" arises because the voltage at the source of Q1 becomes higher than the voltage of its substrate
(ground), thereby increasing the required gate electrode voltage for turning this transistor "on", i.e., thereby increasing its threshold voltage during operation. This increase in threshold voltage during operation
("back-gate bias effect") prevents Q1, from being turned "on" properly unless the drains and gates of NOR-gate load transistors (Q5, Q3) of the previous stages are connected to a relatively high voltage supply, typically +12 volts.
Specifically, when the output drive
transistor Q2 is "off" and the output load transistor Q1 is "on", then the potential of the output terminal12 tends towards VDD, thereby undesirably tending to shut "off" this output load transistor Q1 by virtue of the back-gate bias effect on its threshold, unless the voltage applied to its gate electrode is increased above VDD by a higher drain voltage supply (VGG = 12 volts) to Q5. For example, if the threshold of Q1 is 1.2 volts under the condition of zero "back-gate bias", i.e., when the source of Q1 is at the same ("ground")
potential as that of the semiconductor substrate, then this threshold will rise to as much as about 3 volts when the source of Q1 is at a potential of 4 or 5 volts , i . e , when Q 1 itself is "on" . Accordingly, since the load transistor Q5, which is then also "on", suffers from this same back-gate bias threshold effect, the source potential of Q5 will not rise to the required voltage of about 3 volts necessary to keep Q1 "on" unless the drain of Q5 be supplied at considerably more than 5 volts, or unless Q5 is a depletion mode N-MOS transistor with its gate electrode connected to its source. But even if Q5 is a depletion mode device
which supplies 5 volts to the gate of Q1, the source of the output load transistor Q1 when Q1 is on will not be able to rise to much above 2 (=5-3) volts, instead of a desired 3 or more volts. The Q1 source voltage can be increased to 3 or more volts if the supply to the drain of Q1 and to the drain (and gate) of Q5 is
raised to say 12 volts. Such a high voltage supply requires an additional voltage supply (i.e., +12 volts as well as +5 volts), and also results in undesirable power dissipation during operation. Accordingly, it would be desirable to have a tri-state MOS buffer circuit which does not suffer from these problems.
Summary of the Invention
A tri-state buffer circuit (FIGS. 3 and
4) in MOS technology is in the form of a pair of
NOR-gates feeding an output MOS load transistor (M1) whose high current (source-drain) path is connected in series with that of an output MOS driver transistor
(M2). Each NOR-gate includes a relatively low β MOS load transistor (M3 , M5) in series with a pair of
relatively high β MOS driver transistors connected in parallel (M4,
, M6 , M6). The invention is
characterized in that the threshold voltage of the output load transistor (M1) is intermediate the threshold voltage of the NOR-gate load depletion mode transistors (M3, M5) and the threshold voltage of the driver
enhancement mode transistors (M2, M4,
, M6 ,
M6) of both the output device and the NOR-gates. Thus, three different threshold voltages (all measured under zero back-gate bias) are present in the circuit. These three different threshold voltages result from at least three correspondingly different doping levels in the channel (gate) regions of the respective transistors. In this way, a single relatively low voltage power supply, typically about +5 volts (in N-MOS technology), can be used for operating the buffer circuit with a satisfactory output level.
Brief Description of the Drawing
FIG. 1 is an electrical block diagram of a tristate logic buffer circuit, useful for describing its operation in the prior art;
FIG. 2 is a circuit diagram of a prior art tristate buffer circuit in MOS technology;
FIG. 3 is a circuit diagram of an MOS tri-state non-inverting buffer circuit in accordance with a specific embodiment of the invention; and
FIG. 4 is a circuit diagram of an MOS tri-state inverting buffer circuit in accordance with another
specific embodiment of the invention.
Transistors in FIGS. 3 and 4 (N-MOS technology) that have channel regions doped with acceptor impurities (enhancement mode) are so indicated by the "plus" signs along the corresponding transistor channels in the drawing; on the other hand, transistors that have channel regions doped with donor impurities (depletion mode) are so
indicated by "minus" signs along the corresponding
transistor channels in the drawing; and transistors with channels that are non-doped are so indicated by the lack of either such "plus" or "minus" signs along the corresponding channels. By "non-doped" is meant either that the channel is not subjected to impurity introduction beyond those impurities originally present in the semiconductor wafer or that the channel is doped only lightly as compared with the doping of the channel of an enhancement or depletion mode transistor.
Detailed Description
Only for the sake of definitions, the buffer circuit illustrated in FIG. 3 is assumed to be in N-MOS technology. As shown in FIG. 3, a signal source 13
is connected to the gate electrodes of both the
transistors and M . A local input signal terminal 14.5



is connected to the gate electrode of transistor M4 whose high current (source-drain) path is in parallel with that of . The gate electrode of transistor M6 is connected to the common drain node N4 of transistors M4 and . This


common drain node N4 is connected through the high current (source-drain) path of transistor M3 to a voltage source VDD of typically +5 volts. Similarly, the common drain node N6 of transistors M6 and
g is connected through the high current path of transistor M5 to the voltage
source VDD. The gate electrode of each of the transistors M3 and M5 is connected to the respective source terminal of each of these transistors. Finally, the gate electrode of transistor M1 is connected to the node N6; the gate
electrode of transistor M2 is connected to the node N4; and the high-current paths of M1 and M2 are mutually connected in series, the resulting common node N1 between M1 and M2 being connected to the output terminal 12 on the common data bus line 11. The transistor M1 serves as a "load" during operation and the transistor M2 serves as the
"driver" of said "load". Typical values of the parameters of transconductance β and threshold voltage VT (under zero back-gate bias) are:

Transistor β(10-6 amps/volt2) VT (volts)

M1 (non-doped channel) 400 0.1 M2 (enhancement) 2200 1.2

M3 (depletion) 50 -4.5

M4 (enhancement) 600 1.2

M5 (depletion) 50 -4.5

M6 (enhancement) 600 1.2

As seen from the above listing of parameters, the transconductance β of the output driver transistor M2 is higher than that of the output load transistor M1 , but this may not be essential. The respective values of
transconductance β are achieved by suitable choices of the ratio of channel width to length, as known in the art; the respective values of threshold voltage VT are obtained by suitable impurity doping of the semiconductor gate regions of the respective channels, as by ion implantation
techniques known in the art. This channel impurity doping can, for example, be achieved by using known masking techniques with apertures over those gate regions where the impurity is desired to be implanted during an ionimplantation step, so that only those transistors with channels underlying unmasked (apertured) gate regions will have their thresholds altered by the implantation step.
In order to understand the operation of
the circuit shown in FIG. 3, first consider the case where the control signal 13 is "high" in voltage level (digital "1") due to the presence of a "1" or a "0"
signal level on the common data bus line 11 actively present from another local signal source. In this case, this control signal puts both the high 8 transistors and into their "on" conditions, thereby
bringing both the nodes N4 and N6 to ground
potential, i.e., "low" potential. This puts both the transistors M1 and M2 into their "off" conditions,
regardless of the conditions of the low β transistors M3 and M5 in series therewith, and regardless of the
conditions of the transistors M4 and M6 in parallel
therewith. Accordingly, the node N1 then is controlled solely by the voltage on line 11, regardless of the local input signal 14, i.e., regardless of the "on" or "off" conditions of M4 and M6. Thus, a control signal 13
which is "high" prevents the passage of local signal 14 to the common data bus line 11, as desired.
Turning to the case where the control signal 13 is "low", i.e., all other local signal sources (buffers) connected to line 11 are "floating" (outputs are in high impedance state); in this case both of the transistors M4 and are thus "off". Accordingly the voltages at
nodes N4 and N6, and hence the voltage on the gate
electrodes of M1 and M2, respectively, depend upon the "on" or "off" conditions of transistors M4 and M6.
If the local input signal 14 is then
"high" (digital "1"), then the high β transistor M4 is "on", thereby bringing the potential of node N4 down to substantially ground ("low") potential and hence putting both the transistors M2 and M6 into their respective
"off" conditions. On the other hand, the potential of the node N6 will then be controlled by the condition of transistor M5, since then both transistors M6 and
are "off". At this time the potential of node N6 will thus be about +5 volts since the threshold voltage of transistors M5 is so negative even in the presence of the increase in threshold to typically about -2 or -3 volts, caused by the resulting back-gate bias, instead of the -4.5 volts under zero back-gate bias. Accordingly, the node N6 being at +5 volts, the output load
transistor M1 will be "on", and very strongly so,
because its threshold is only a fraction of a volt under zero back-gate bias and is less than +2 volt (and hence much less than +5 volt) under a back-gate bias of as much as 4 or 5 volts. Thus, the potential of N1 and hence of the source of the output load transistor M1 , and
hence also the output voltage at the output terminal 12, will then rise to at least about (5-2)=3 volts. On the other hand, with a 1.2 volt threshold for this output load transistor under zero back-gate bias, this output voltage would be only about 2 volts or less.
Accordingly, the advantage of using a relatively low
(i.e., lower than that of M2) but positive threshold voltage for the output load transistor M1 is apparent:
it provides a wider margin of distinction in output
voltage level between an output "0" (=0 volts) and an output "1" (=3 volts or more).

Consider next the case where the control
signal 13 is still "low" (no signals on the line 11 from other sources) and the local signal 14 is also "low"
(digital "0"); then, since both transistors M4 and

are "off", the node N4 will be at a voltage about equal to VDD = 5 volts. Accordingly, both the NOR-gate driver transistor M6 and the output driver M2 will be "on";
so that in particular the node N6 will be substantially at ground potential, thereby keeping the output load transistor M1 in its "off" condition, while the output driver transistor M2 will then be "on". Thus, the
output terminal 12 will be at ground ("low") potential, that is, an output digital "0" results in response to a local input signal 14 of digital "0", as desired.
Turning to the tri-state MOS buffer circuit shown in FIG. 4, this buffer circuit is obtained by modifying the circuit of FIG. 3 to connect the node N4 to the gate electrode of transistor M1 instead of M2 and the node N6 to the gate electrode of M2 instead of M1. In this way, when the control signal does not disable the buffer circuits, a local input signal at input terminal 14.5 of digital "1" results in an inverted output voltage at the output
terminal 12, or a digital "0" (instead of digital "1" as in the buffer circuit of FIG. 3) , and a local input of digital "0" results in an output of digital "1". Thus, the buffer circuit of FIG. 4 inverts the local input signal so long as the control signal source 13 does not put out its disabling signal, otherwise (when the control signal is disabling) the output of this buffer circuit is electrically
"floating" just as in the case of the circuit shown in FIG. 3.
It should be noted that the arrangement of transistors M3 , M4 and
constitutes a NOR-gate, as does the arrangement of transistors M5, M6 , and .


Specifically, the node N4 is "high" in voltage only if both transistors M4 and are "off", that is, only
if neither the local input signal 14 nor the control signal from the control signal source 13 is "high". If either such signal is "high", then the corresponding transistor M4 or
is "on", thereby connecting the
node N4 to ground ("low") potential through a high β
(high conductance) path. Conversely, the only way that the node N4 can be "high" (digital "1") is by having both transistors M4 and
in the "off" condition,
that is, by having the voltage of both the input signals 13 and 14 "low" (digital "0"). Thus, the output at node N4 of the arrangement M3, M4, and corresponds


to that of a NOR-gate; and similarly for the arrangement M5, M6, and
.
As noted above, it is advantageous that the threshold voltage of the output load transistor M1 be lower than those of the output driver transistor M2 and the NORgate driver transistors (M4,
, M6,
) , in order to promote wider margin of output level distinction between the "on" and "off" conditions of M1. On the other hand, it is also advantageous that the threshold voltages of the load transistors M3 and M5 in the NOR-gates be still lower than that of the load transistor M1 in the output, in order to avoid undesirable threshold drops across these NOR-gate loads even under operating conditions of back-gate bias which would otherwise prevent proper turn-on of the output load transistor M1. Thus, the threshold voltage of the output load transistor M1 should be intermediate between that of the NOR-gate load transistors (M5 and M3) and that of the NOR-gate drive transistors (M4 , , M6, ) .



Although this invention has been described in detail in terms of specific illustrations, various
modifications can be made without departing from the scope of the invention. For example, the output load transistor can have non-vanishing impurity doping (as by ion
implantation) in its gate (channel) region in conjunction with a suitable semiconductor wafer substrate doping level, in order to obtain substantially the same threshold voltage as in the case of the undoped channel region. Also regarding technology, instead of N-MOS transistors, P-MOS (P channel) transistors can be used by changing the polarity of the voltage supply and correspondingly
changing the threshold voltages of the various transistors by suitable impurity doping.