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Machine translation
1. (WO1979000684) ISOLATION OF INTEGRATED CIRCUITS BY STEPWISE SELECTIVE ETCHING,DIFFUSION AND THERMAL OXIDATION
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/1979/000684    International Application No.:    PCT/US1979/000102
Publication Date: 20.09.1979 International Filing Date: 26.02.1979
IPC:
H01L 21/74 (2006.01), H01L 21/762 (2006.01)
Applicants:
Inventors:
Priority Data:
882802 02.03.1978 US
Title (EN) ISOLATION OF INTEGRATED CIRCUITS BY STEPWISE SELECTIVE ETCHING,DIFFUSION AND THERMAL OXIDATION
(FR) ISOLATION DE CIRCUITS INTEGRES PAR ATTAQUE CHIMIQUE SELECTIVE, DIFFUSION ET OXYDATION THERMIQUE, SUCCESSIVEMENT
Abstract: front page image
(EN)A method of isolating portions of integrated circuits which permits closely packed structures. A semiconductor wafer is provided with a substrate of one conductivity type, a first layer of opposite conductivity type and high impurity concentration formed thereon, and a second layer of either conductivity type but lower concentration formed over the first layer. The major surfaces of the semiconductor layers are parallel to the (110) plane. Narrow grooves with sidewalls in the (111) plane are etched into the first layer. A shallow diffusion of impurities of the same conductivity type as the first layer is performed in the sidewalls and bottom of the grooves which permits the first layer to be contacted from the surface of the second layer. The groove is then etched further until it extends into the underlying substrate. Impurities of the same conductivity type as the substrate are diffused into the bottom and sidewalls of the grooves. The concentration of these impurities is chosen so that a chanstop region is formed in the substrate without appreciably affecting electrical conductivity between the first layer and the regions formed by the previous diffusion.
(FR)Methode d"isolation de portions de circuits integres permettant d"obtenir des structures etroitement serrees. Une plaquette gaufree a semi-conducteur est pourvue d"un substrat d"un type de conductivite, d"une premiere couche de conductivite contraire et a forte concentration d"impuretes formee sur ledit substrat, et d"une seconde couche de l"une ou l"autre des conductivites mais a concentration moins elevee formee sur la premiere couche. Les surfaces principales des couches a semi-conducteur sont paralleles au plan (110). Des rainures etroites ayant des parois laterales dans le plan (111) sont gravees par attaque chimique dans la premiere couche. Une diffusion superficielle des impuretes de meme conductivite que la premiere couche s"effectue au niveau des parois laterales et du fond des rainures, ce qui permet a la premiere couche d"etre en contact avec la surface de la seconde couche. Les rainures sont ensuite prolongees par attaque chimique jusqu"a atteindre le substrat sous-jacent. Les impuretes de meme conductivite que le substrat sont diffusees dans le fond et les parois laterales des rainures. La concentration de ces impuretes est choisie de telle sorte qu"une region "chanstop" (delimitation) se forme dans le substrat sans affecter sensiblement la conductivite electrique entre la premiere couche et les regions formees par la diffusion anterieure.
Designated States:
Publication Language: English (EN)
Filing Language: English (EN)