Traitement en cours

Veuillez attendre...

Paramétrages

Paramétrages

Aller à Demande

1. JP2010096770 - SEMICONDUCTOR TEST APPARATUS

Office
Japon
Numéro de la demande 2010008199
Date de la demande 18.01.2010
Numéro de publication 2010096770
Date de publication 30.04.2010
Numéro de délivrance 4977217
Date de délivrance 20.04.2012
Type de publication B2
CIB
G01R 31/319
GPHYSIQUE
01MÉTROLOGIE; TESTS
RMESURE DES VARIABLES ÉLECTRIQUES; MESURE DES VARIABLES MAGNÉTIQUES
31Dispositions pour tester les propriétés électriques; Dispositions pour la localisation des pannes électriques; Dispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
28Test de circuits électroniques, p.ex. à l'aide d'un traceur de signaux
317Tests de circuits numériques
3181Tests fonctionnels
319Matériel de test, c. à d. circuits de traitement de signaux de sortie
CPC
G01R 31/3191
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
3181Functional testing
319Tester hardware, i.e. output processing circuit
31903tester configuration
31908Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
3191Calibration
G01R 31/31922
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
3181Functional testing
319Tester hardware, i.e. output processing circuit
31917Stimuli generation or application of test patterns to the device under test [DUT]
31922Timing generation or clock distribution
G01R 31/31937
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
3181Functional testing
319Tester hardware, i.e. output processing circuit
3193with comparison between actual response and known fault free response
31937Timing aspects, e.g. measuring propagation delay
G01R 31/28
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
G01R 25/00
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
25Arrangements for measuring phase angle between a voltage and a current, or between voltages or currents
Déposants ADVANTEST CORP
株式会社アドバンテスト
Inventeurs OHASHI MASATOSHI
大橋 正俊
OKAYASU TOSHIYUKI
岡安 俊幸
Mandataires 渡邊 喜平
Données relatives à la priorité 2002168304 10.06.2002 JP
Titre
(EN) SEMICONDUCTOR TEST APPARATUS
(JA) 半導体試験装置
Abrégé
(EN)

PROBLEM TO BE SOLVED: To perform an excellent failure/no-failure test of devices by measuring the cross point of a differential clock signal output from a device under test (DUT) and the timings of two data signals to obtain a relative phase difference between the two signals.

SOLUTION: There are provided a differential signal timing measuring means that outputs cross point information Tcross obtained by measuring the timing of the cross point of one differential output signal output from the DUT; a non-differential signal timing measuring means that outputs data change point information Tdata obtained by measuring a transition timing at which the logic of the other non-differential output signal output from DUT transitions; a phase difference calculating means that outputs a phase difference T obtained by calculating the relative phase difference between the cross point information Tcross obtained by measuring the two output signals at the same time and the data change point information Tdata; and a failure/no-failure test means receptive of the phase difference T for performing, based on a predetermined threshold value, a failure/no-failure test in the relative phase relationship of DUT.

COPYRIGHT: (C)2010,JPO&INPIT


(JA)

【課題】 DUTから出力される差動のクロック信号のクロスポイントとデータ信号の両信号のタイミングを測定し、両信号間の相対的な位相差を求めることで良好なデバイスの良否判定が実現可能とする。
【解決手段】 DUTから出力される一方の差動の出力信号のクロスポイントのタイミングを測定して得たクロスポイント情報Tcrossを出力する差動信号タイミング測定手段と、DUTから出力される他方の非差動の出力信号の論理が遷移する遷移タイミングを測定して得たデータ変化点情報Tdataを出力する非差動信号タイミング測定手段と、両出力信号を同時に測定して得たクロスポイント情報Tcrossとデータ変化点情報Tdataとの両者間の相対的な位相差を求めて得た位相差ΔTを出力する位相差算出手段と、位相差ΔTを受けて良否判定を行う所定のしきい値に基づいてDUTの相対的な位相関係の良否を判定する良否判定手段とを備える。
【選択図】 図1