Certains contenus de cette application ne sont pas disponibles pour le moment.
Si cette situation persiste, veuillez nous contacter àObservations et contact
1. (EP2203974) CIRCUIT D'ENTRÉE POUR UN AMPLIFICATEUR ET PROCÉDÉ DE CONCEPTION ASSOCIÉ
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique
Claims

1. A circuit comprising;

a transistor (14) having an input electrode;

an input matching network (12) having an input (13) for being fed by an input signal and having transistor an output (16) connected to the input electrode of the transistor (14); and

a power level sensing circuit (18) for being fed by the input signal,

wherein the input matching network (12) is responsive to the power level sensing circuit (18) to configure the input matching network (12) with a first input impedance when the power level sensing circuit (18) senses that the input signal has a first power level, and to configure the input matching network (12) with a second input impedance different from the first input impedance when the power level sensing circuit (18) senses that the input signal has a second power level, the said first power level being lower than the said second power level,

and characterised in that:

the transistor (14) is a gallium nitride transistor having a field plate or gamma gate,

the input matching network (12) includes:

i) a pair of electrical components (L1, L2); and

ii) at least one switch (20, 22),

the at least one switch (20, 22) is configured to operate in response to the power level sensing circuit (18) to:

i) electrically decouple one of the pair of electrical components (L1, L2) from the input matching network (12) at said second power level; and

ii) electrically couple said one of the pair of electrical components (L1, L2) to the input matching network (12) at said first power level, and

the first input impedance is matched for a small-signal input signal and the second input impedance is rotated clockwise between about 10 degrees and about 15 degrees from the first impedance on the Smith chart; the first input impedance corresponding to the first power level at which the transistor exhibits soft compression in the power transfer characteristic and the second input impedance corresponding to the second power level at which the soft compression is eliminated or significantly reduced.


  2. The circuit recited in claim 1, wherein the input matching network (12) is configured such that:

the input matching network (12) has a first inductor (L1) serially coupled between the input signal and the input electrode of the transistor (14) when the power level sensing circuit (18) senses that the input signal has the second power level; and

the input matching network (12) has a second inductor (L2) serially coupled between the input signal and the input electrode of the transistor (14) when the power level sensing circuit (18) senses that the input signal has the first power level.


  3. The circuit recited in claim 2 wherein a gate electrode (G) of the transistor (14) serves as its input electrode.
  4. The circuit recited in claim 1, wherein the electrical components are inductors (L1, L2) having different inductances.