Traitement en cours

Veuillez attendre...

Paramétrages

Paramétrages

Aller à Demande

1. CN1774802 - Circuit device with at least partial packaging and method for forming

Office Chine
Numéro de la demande 200480010401.X
Date de la demande 06.04.2004
Numéro de publication 1774802
Date de publication 17.05.2006
Numéro de délivrance 100413065
Date de délivrance 20.08.2008
Type de publication C
CIB
H01L 23/48
HÉLECTRICITÉ
01ÉLÉMENTS ÉLECTRIQUES FONDAMENTAUX
LDISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS
23Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
48Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
CPC
H01L 21/561
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
561Batch processing
H01L 21/565
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
565Moulds
H01L 21/568
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
568Temporary substrate used as encapsulation process aid
H01L 23/3107
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
31characterised by the arrangement ; or shape
3107the device being completely enclosed
H01L 23/3128
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
31characterised by the arrangement ; or shape
3107the device being completely enclosed
3121a substrate forming part of the encapsulation
3128the substrate having spherical bumps for external connection
H01L 23/50
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements
50for integrated circuit devices, ; e.g. power bus, number of leads
Déposants Freescale Semiconductor Inc.
飞思卡尔半导体公司
Inventeurs Leal George R.
乔治·利尔
Zhao Jie-hua
赵杰华
Prack Edward R.
艾德华·R·普拉克
Wenzel Robert J.
罗伯特·J·温策尔
Sawyer Brian D.
布莱恩·D·索耶
Wontor David G.
大卫·G·汪托尔
Mangrum Marc A.
马克·阿兰·曼格拉姆
Mandataires zhang gao
中国国际贸易促进委员会专利商标事务所
Données relatives à la priorité 10418790 18.04.2003 US
Titre
(EN) Circuit device with at least partial packaging and method for forming
(ZH) 至少具有部分封装的电路器件及其形成方法
Abrégé
(EN)
In one embodiment, circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). In this embodiment, at least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device (115) is placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). In this embodiment, conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.

(ZH)

在一个实施例中,将电路器件(15)设置在导电层(10)的开口内,然后用包封(24)部分包封,使得电路器件(15)的有源面与导电层(10)共面。在该实施例中,可以使用导电层(10)的至少一部分作为参考电压平面(例如接地平面)。在一个实施例中,将电路器件(15)设置导电层(100)上,使得电路器件(115)的有源面处于导电层(100)和电路器件(115)的相反表面之间。在该实施例中,导电层(100)具有至少一个开口(128),以暴露电路器件(115)的有源面。对于某些实施例来说,包封(24,126,326)可以是导电的,对于其它实施例来说,是非导电的。