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1. (WO2014164062) PROCÉDÉ DE FABRICATION D'UN COMPOSANT NAND VERTICAL EN UTILISANT LA GRAVURE SÉQUENTIELLE DE PILES MULTICOUCHES
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

WHAT IS CLAIMED IS:

1. A method of making a vertical NAND device, comprising:

forming a lower portion of a memory stack over a substrate;

forming a lower portion of memory openings in the lower portion of the memory stack;

at least partially filling the lower portion of the memory openings with a sacrificial material;

forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material;

forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings;

removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings extending through the upper and the lower portions of the memory stack; and

forming a semiconductor channel in each continuous memory opening.

2. The method of claim 1, wherein the lower and the upper portions of the memory stack comprise alternating insulating and sacrificial layers, and wherein the sacrificial material layers are removed and replaced with a memory film and control gate electrodes.

3. The method of claim 1, wherein the lower and the upper portions of the memory stack comprise alternating insulating and control gate material layers.

4. The method of claim 3, further comprising forming a memory film which comprises at least one charge storage region located between blocking and tunneling dielectric layers in each continuous memory opening prior to the step of forming the semiconductor channel.

5. The method of claim 4, wherein:

the tunnel dielectric layer is located adjacent to the semiconductor channel;

the charge storage region is located adjacent to the tunnel dielectric layer;

the blocking dielectric layer is located adjacent to the charge storage region;

each control gate material layer comprises a control gate electrode which extends substantially parallel to a major surface of the substrate; and

the control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level.

6. The method of claim 5, wherein:

the semiconductor channel has a U-shaped side cross section;

two wing portions of the U-shaped semiconductor channel which extend substantially perpendicular to the major surface of the substrate are connected by a connecting portion of the semiconductor channel which extends substantially parallel to the major surface of the substrate; and

an insulating fill is located over the connecting portion and separating two wing portions of the U-shaped semiconductor channel.

7. The method of claim 5, wherein the device comprises at least a 3x3 array of NAND strings, the first control gate electrode and the second control gate electrode are continuous in the array, and the first control gate electrode and the second control gate electrode do not have an air gap or a dielectric filled trench in the array.

8. The method of claim 5, wherein:

each semiconductor channel has a pillar shape; and

the entire pillar-shaped semiconductor channel extends substantially perpendicularly to the major surface of the substrate.

9. The method of claim 1, wherein the lower portion of the memory openings is formed by etching the lower portion of the memory stack using a first hard mask, and the upper portion of the memory openings is formed by etching the upper portion of the memory stack using at least one second hard mask.

10. The method of claim 9, wherein etching the upper portion of the memory stack and removing the sacrificial material occur in a same etching step or in different etching steps.

11. The method of claim 1 , wherein:

the lower and the upper portions of the memory stack comprise alternating insulating and polysilicon control gate material layers; and

at least partially filling the lower portion of the memory openings with a sacrificial material comprises selectively growing a germanium sacrificial material using exposed edges of the polysilicon control gate material layers in the lower portion of the memory openings as a seed until the germanium sacrificial material completely fills the lower portion of the memory openings.

12. The method of claim 11, wherein:

a top layer of the lower portion of the memory stack comprises a top insulating layer; the top layer is thinner than other insulating layers in the lower portion of the memory stack;

selectively growing the germanium sacrificial material comprises growing the germanium sacrificial material such that it does not grow on an upper surface of the top insulating layer; and

removing the sacrificial material comprises selectively etching the germanium sacrificial material from the lower portion of the memory openings.

13. The method of claim 11, wherein:

forming the upper portion of the memory openings comprises etching the upper portion of the memory stack using a carbon hard mask followed by removing the carbon hard mask by oxygen containing plasma ashing;

the oxygen containing plasma ashing converts the germanium sacrificial material exposed in the upper portion of the memory openings to germanium oxide; and

removing the sacrificial material comprises selectively wet etching the germanium oxide sacrificial material using a peroxide containing etching liquid.

14. The method of claim 6, further comprising:

forming a connecting region comprising a silicon germanium or germanium material under the lower portion of the memory stack; and

exposing the connecting region at a bottom of the lower portion of the memory openings.

15. The method of claim 14, wherein:

at least partially filling the lower portion of the memory openings with a sacrificial material comprises selectively growing a germanium sacrificial material using the connecting region exposed in the lower portion of the memory openings as a seed until the germanium sacrificial material completely fills the lower portion of the memory openings; and

removing the sacrificial material comprises selectively etching the germanium sacrificial material from the lower portion of the memory openings.

16. The method of claim 15, further comprising:

removing the connecting region by selectively etching the connecting region during the step of selectively etching the germanium sacrificial material or in subsequent selective etching step to leave a connecting opening; and

forming the connecting portion of the semiconductor channel in the connecting opening during the step of forming the semiconductor channel.

17. The method of claim 1, wherein at least partially filling the lower portion of the memory openings with a sacrificial material comprises completely filling the lower portion of the memory opening with a spin-on sacrificial carbon or polymer material.

18. The method of claim 1, wherein at least partially filling the lower portion of the memory openings with a sacrificial material comprises:

completely filling the lower portion of the memory opening with a spin-on self decomposable polymer material;

forming a sacrificial porous layer over the polymer material; and

heating the polymer material to decompose the polymer material into a vapor which flows out of the lower portion of the memory opening through the sacrificial porous layer to leave an air gap in the lower portion of the memory openings under the sacrificial porous layer.

19. The method of claim 18, wherein:

the sacrificial porous layer comprises porous silicon oxide; and

removing the sacrificial material comprises etching the porous silicon oxide during the step of forming the upper portion of the memory openings by etching the upper portion of the memory opening in the upper portion of the memory stack.

20. The method of claim 1, wherein at least partially filling the lower portion of the memory openings with a sacrificial material comprises forming a non-conformal sacrificial layer over the lower portion of the memory openings such that the sacrificial layer pinches off a top of the lower portion of the memory openings and leaves an air gap below it in the lower portion of the memory openings.

21. The method of claim 20, wherein:

forming the non-conformal sacrificial layer comprises forming a sacrificial silicon nitride layer by high pressure CVD over the entire lower portion of the memory stack and in the top of the lower portion of the memory openings, followed by planarization or etch-back to leave the sacrificial silicon nitride only in the top of the lower portion of the memory openings; and

removing the sacrificial material comprises either: (i) etching the silicon nitride during the step of forming the upper portion of the memory openings by etching the upper portion of the memory openings in the upper portion of the memory stack, or (ii) etching the silicon nitride using a hot phosphoric acid selective wet etch after the step of forming the upper portion of the memory openings.

22. The method of claim 1, further comprising widening a diameter of a top part of the lower portion of the memory openings.