Traitement en cours

Veuillez attendre...

PATENTSCOPE sera indisponible durant quelques heures pour des raisons de maintenance le mardi 26.10.2021 à 12:00 PM CEST
Paramétrages

Paramétrages

Aller à Demande

1. WO2020167117 - ARCHITECTURE DE CIRCUIT INTÉGRÉ SÉCURISÉE

Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

[ EN ]

CLAIMS

1 . Integrated circuit hardware arrangement comprising one or more components (2; 2A-2G), each of the one or more components (2; 2A-2G) comprising embedded circuitry (21 -31) allowing run-time execution of a micro-agent, and an interface to an agent network (4) interconnecting the one or more components (2; 2A-2G), the micro-agent being arranged

- to determine a signature of the associated component (2; 2A-2G),

- to communicate via the agent network (4) with further connected micro-agents being executed in further ones of the one or more components (2; 2A-2G) of the integrated circuit hardware arrangement (1), and

- to detect a possible attack by analysing the determined signature

wherein the one or more components (2; 2A-2G) in combination with the micro-agent being executed, form a basic building block of the integrated circuit hardware arrangement (1 ).

2. Integrated circuit hardware arrangement according to claim 1 , wherein each of the one or more components (2; 2A-2G) comprises a control unit (22) which is arranged to allow the microagent to communicate with the further micro-agents.

3. Integrated circuit hardware arrangement according to claim 1 or 2, wherein each of the one or more components (2; 2A-2G) comprises a self-organised cognitive map (23) which is arranged to store data associated with the signature determined by the micro-agent.

4. Integrated circuit hardware arrangement according to claim 1 , 2 or 3, wherein each of the one or more components (2; 2A-2G) comprises an interface to a data network (3), the data network (3) providing a control and data interconnection between the one or more components (2; 2A-2G).

5. Integrated circuit hardware arrangement according to claim 1 , 2 or 3, wherein specific ones of the one or more components (2; 2A-2G) comprise an interface to a supply network (5), the supply network (5) being arranged to supply power, clock and/or reset signals to the specific ones of the one or more components (2; 2A-2G).

6. Integrated circuit hardware arrangement according to any one of claims 1 -5, wherein the micro-agent is further arranged to enter a response on attack state (13) upon detection of a possible attack, the response on attack state (13) comprising active control of the associated component (2; 2A-2G).

7. Integrated circuit hardware arrangement according to any one of claims 1 -6, wherein the micro-agent is further arranged:

- to communicate with the further micro-agents via the agent network (4),

- to collect signatures from the further micro-agents,

- to detect a possible attack by analysing the collected signatures, and

- to send control data [Actions and Status] to the further micro-agents via the agent network (4).

8. Integrated circuit hardware arrangement according to claim 7, wherein the micro-agent is further arranged to exchange contracting data with the further micro-agents via the agent network (4).

9. Integrated circuit hardware arrangement according to any one of claims 1-8, wherein the micro-agent is arranged to determine the signature in an asynchronous manner.

10. Integrated circuit hardware arrangement according to any one of claims 1-9, wherein the embedded circuitry comprises a custom logic unit (21) interfacing with logic gates of the component (2; 2A-2G),

wherein the micro-agent is further arranged to determine the signature based on determination of logic gate related parameters.

11. Integrated circuit hardware arrangement according to claim 10, wherein the determination of logic gate related parameters comprises one or more of current behaviour measurement, delay measurement, integrity check, side channel behaviour measurement.

12. Integrated circuit hardware arrangement according to any one of claims 10-11 , wherein the micro-agent is further arranged to determine a possible hardware attack by analysing the determined signature.

13. Integrated circuit hardware arrangement according to any one of claims 1-9, wherein the micro-agent is further arranged to execute additional functionality for detecting software attacks.

14. Integrated circuit hardware arrangement according to claim 13, wherein the additional functionality is arranged to collect statistical data associated with the integrated circuit hardware arrangement (1).

15. Integrated circuit hardware arrangement according to any one of claims 1-14, wherein the one or more components (2; 2A-2G) of the integrated circuit hardware arrangement (1) comprises one or more of the following:

an iContainer component (2A) arranged to store data [e.g. using semiconductor memory elements]; an iBrick component (2B) comprising digital logic [e.g. CPU and related elements];

an iConnect component (2C) comprising interface and control circuitry;

an iRouter component (2D) arranged to control data flow between the one or more components; an iSupply component (2E) arranged to manage clock, power and reset lines;

an iAnalog component (2F) comprising analog circuitry arranged to interface with external analog inputs (e.g. sensor inputs);

an Debug component (2G) arranged to perform debugging tasks.

16. Integrated circuit hardware arrangement according to claim 15, wherein the integrated circuit hardware arrangement (1) further comprises one or more sensor units (73, 74) connected to an iAnalog component (2F).

17. Integrated circuit hardware arrangement according to any one of claims 1 -16, wherein the one or more components (2; 2A-2G) are arranged as a system on a chip (SoC, 7).