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1. WO2008004158 - procédé et système pour la configuration d'un périphérique matériel

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CLAIMS:

1. A method for re-configuration of a hardware peripheral (20; 30) performing at least one function for a system with at least one processor, wherein the method comprises: transferring a set of configuration parameters for the hardware peripheral (20; 30) from an at least one first data source (22; 31) to the hardware peripheral (20; 30) via an at least one first DMA channel (24; 33); and re-configuring the hardware peripheral (20, 30) with the set of configuration parameters.

2. The method according to claim 1, wherein the method further comprises transferring data to be processed by the hardware peripheral (20, 30) from an at least one second data source (11, 22, 31) to the hardware peripheral (20, 30) via an at least one second DMA channel (23, 33).

3. The method according to claim 1 or 2, wherein the method further comprises transferring data processed by the hardware peripheral (20, 30) to an at least one data destination (11, 22, 31) from the hardware peripheral (20, 30) via an at least one third DMA channel (25, 34).

4. The method according to one of the claim 1 to 3, further comprising setting up the hardware peripheral (20; 30) by assembling at least one set of configuration parameters for the hardware peripheral (20; 30) in at least one data pre-processing means (21); and storing the least one set of configuration parameters in at least one memory means (22, 31).

5. The method according to claim 4, wherein in the assembling step the at least one set of configuration parameters is stored in a processor (21) memory.

6. The method according to claim 4, wherein in the storing step the at least one set of configuration parameters is stored in a system memory (22; 31, 32).

7. The method according to one of the claims 3 to 6, wherein in the assembling step at least one finite state machine (15) is configured to generate a plurality of sets of configuration parameters in a predetermined order.

8. The method according to one of the preceding claims, wherein the assembling step further comprises arranging more than one set of configuration parameters and the data to be processed as a linked list.

9. A hardware peripheral (20; 30) for performing at least one function for a system with at least one processor, wherein the hardware peripheral (20; 30) is configured to receive a set of configuration parameters for re-configuration of the at least one function from at least one first data source (22; 31) via at least one first DMA channel (24; 33); and wherein the hardware peripheral (20; 30) is configured to be re-configured with the received set of configuration parameters.

10. The hardware peripheral (20; 30) according to claim 9, wherein the hardware peripheral (20; 30) comprises means for transferring data to be processed to the hardware peripheral (20; 30) from at least one second data source (11; 22; 31) to the hardware peripheral (20; 30) via at least one second DMA channel (23; 33).

11. The hardware peripheral (20; 30) according to claim 9 or 10, wherein the hardware peripheral (20; 30) comprises means for transferring data processed from the hardware peripheral (20; 30) to at least one data destination (12; 22; 32) via at least one third DMA channel (25; 34).

12. The hardware peripheral (20, 30) according to one of the claims 9 to 11, wherein at least one of the data to be processed and the at least one set of configuration parameters are arranged as respective linked lists in the at least one first data source and second data source, respectively.

13. The hardware peripheral (20; 30) according to one of the claims 9 to 12, wherein the hardware peripheral (20; 30) is a hardware accelerator or a peripheral with a coprocessor behavior.

14. The hardware peripheral (20; 30) according to one of the claims 9 to 13, wherein the hardware peripheral (20; 30) is a GPS hardware accelerator.

15. The hardware peripheral (20; 30) according to one of the claims 9 to 14, wherein the first and second data source and the data destination are located in a single memory such that the first, second, and third DMA channels are connected to a single memory.

16. The hardware peripheral (20; 30) according to claims 15, wherein the single memory is the system memory of the system with the at least one processor.

17. A system for processing a high amount of temporary data, the system comprising at least one processor and a hardware peripheral (20; 30) according to any one of the claims 10 to 16, such that processor load caused by handling of the high amount of temporary data is reduced.

18. The system according to claim 17, wherein the system comprises at least one means (25) for assembling at least one set of configuration parameters for re-configuration of the hardware peripheral (20; 30).