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1. WO2011056852 - CIRCUIT D'ATTAQUE SDBT À HAUTE PERFORMANCE POUR ALIMENTATION ÉVOLUTIVE

Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

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CLAIMS

What is claimed is:

1. An apparatus comprising:

an input stage having a first differential pair of CMOS transistors that receive a differential input signal; and a second differential pair of CMOS transistors coupled to the first differential pair;

a first output stage having a first diode-connected bipolar transistor and a second diode-connected bipolar transistor; wherein each of the first and second diode-connected bipolar transistors is coupled to one of the CMOS transistors of the second differential pair;

a second output stage having a first set of bipolar transistors; wherein each bipolar transistor of the first set is coupled to the first diode -connected bipolar transistor at its base; and a first current mirror coupled to the collector of at least one of the bipolar transistors of the first set; and

a third output stage having a second set of bipolar transistors; wherein each bipolar transistor of the first set is coupled to the first diode-connected transistor at its base; wherein the collector of at least one bipolar transistor from the second set is coupled to the first current mirror; and wherein a second current mirror is coupled the collector of at least one bipolar transistor of the first set and at least one bipolar transistor of the second set.

2. The apparatus of Claim 1, wherein the first differential pair of CMOS transistors further comprises:

a first NMOS transistor that receives at least a portion of the differential input signal at its gate;

a second NMOS transistor that is coupled to the source of the first NMOS transistor at its source and that receives at least a portion of the differential input signal at its gate; and

a current source that is coupled to the sources of the first and second NMOS transistors.

3. The apparatus of Claim 2, wherein the second differential pair of CMOS transistors further comprises:

a third NMOS transistor that is coupled to at least one of the plurality of diode-connected bipolar transistors at its drain and to the drain of the first NMOS transistor at its gate;

a fourth NMOS transistor that is coupled to at least one of the plurality of diode-connected bipolar transistors at its drain and to the drain of the second NMOS transistor at its gate; and

a second current source that is coupled to the sources of the third and fourth NMOS transistors.

4. The apparatus of Claim 3, wherein the first output stage further comprises:

a first diode-connected PNP transistor that is coupled to at least one of the CMOS transistors at its base and collector;

a second diode-connected PNP transistor that is coupled to at least one of the CMOS transistors at its base and collector;

a first current source that is coupled to the emitter and base of the first PNP transistor; and

a second current source that is coupled to the emitter and base of the second PNP transistor.

5. The apparatus of Claim 4, wherein the first set of bipolar transistors further comprises:

a first PNP transistor that is coupled to the base of at least one of the plurality of diode-connected bipolar transistors at its base and the first current mirror at its collector; and

a second PNP transistor that is coupled to the base of the first PNP transistor at its base and the second current mirror at its collector.

6. The apparatus of Claim 5, wherein the second set of bipolar transistors further comprises:

a first PNP transistor that is coupled to the base of at least one of the plurality of diode-connected bipolar transistors at its base and the second current mirror at its collector; and

a second PNP transistor that is coupled to the base of the first PNP transistor at its base and the first current mirror at its collector.

7. An apparatus comprising signal generating circuitry and a plurality of low voltage differential signal (LVDS) drivers that are each coupled to the signal generating circuitry, wherein each LVDS driver includes:

a positive input terminal that is coupled to the signal generating circuitry;

a negative input terminal that is coupled the signal generating circuitry;

a first supply rail for supplying a voltage;

a second supply rail;

a positive output terminal;

a negative output terminal;

a first NMOS transistor that is coupled to the positive input terminal at its gate and the first supply rail at its drain;

a second NMOS transistor that is coupled to the negative input terminal at its gate and the first supply rail at its drain;

a first current source that is coupled between the sources of the first and second NMOS transistors and the second supply rail;

a third NMOS transistor that is coupled to the drain of the first NMOS transistor at its gate;

a fourth NMOS transistor that is coupled to the drain of the second NMOS transistor at its gate;

a second current source that is coupled to the sources of the third and fourth NMOS transistors;

a first PNP transistor that is coupled to the drain of the third NMOS transistor at its base and collector and the first supply rail at its emitter;

a second PNP transistor that is coupled to the drain of the fourth NMOS transistor at its base and collector and the first supply rail at its emitter;

a third current source that is coupled to the emitter and base of the first PNP transistor; a fourth current source that is coupled to the emitter and base of the second PNP transistor;

a third PNP transistor that is coupled to the first supply rail at its emitter and the base of the first PNP transistor at its base;

a fourth PNP transistor that is coupled to the first supply rail at its emitter, the base of the first PNP transistor at its base, and the negative output terminal at its collector;

a first current mirror that is coupled to the second supply rail and the collector of the third PNP transistor and the positive output terminal;

a fifth PNP transistor that is coupled to the first supply rail at its emitter and the base of the second PNP transistor at its base;

a sixth PNP transistor that is coupled to the first supply rail at its emitter, the base of the second PNP transistor at its base, and the positive output terminal at its collector; and

a second current mirror that is coupled to the second supply rail, the collector of the fifth PNP transistor, and the negative output terminal.

8. A method comprising:

receiving a differential signal by a differential input pair of CMOS transistor, wherein the differential input signal has a state;

mirroring one of a first current and a second current, generated in a first output stage from a supply voltage between about 1.8V and about 3.3V, in a corresponding one of a second output stage and a third output stage based at least in part on the state of differential signal; and generating a differential current at a first output terminal and a second output terminal, wherein direction of the differential current is based at least in part on the state of the differential signal, and wherein the second and third output stages are coupled to each of first and second output terminals.

9. The method of Claim 8, wherein the state of the differential signal further comprises a first state and a second state, and wherein the step of mirroring further comprises: generating the first current in a first diode-connected bipolar transistor for the first state; mirroring the first current in the second output stage for the first state;

generating the second current in a second diode-connected bipolar transistor in the second state; and

mirroring the second current in the third output stage for the second state.

10. The method of Claim 9, wherein the step of generating further comprises:

generating the differential current in a first direction for the first state; and generating the differential current in a second direction for the second state.