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1. (WO2004062093) AMPLIFICATEUR A FAIBLE BRUIT A PORTE COMMUNE A TRAVERSEE RESISTIVE
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

Attorney Docket No. PATENT APPLICATION

080374.0009

IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
(U.S. RECEIVING OFFICE)

SPECIFICATION
accompanying

Application for Grant of Letters Patent

TITLE: COMMON GATE WITH RESISTIVE FEED-THROUGH LOW NOISE AMPLIFIER

PRIORITY DATA
This application claims priority to U.S. provisional application no. 60/435,504, filed December 20, 2002, entitled "Common Gate with Resistive Feedthrough Low Noise Amplifier," which is hereby incorporated by reference for all purposes.

FIELD OF THE INVENTION

[0001] The present invention pertains to the field of amplifiers, and in particular to a common gate low noise amplifier with resistive feed-through for improved noise performance .

080374.0009 WEST 5390628 vl 1 Attorney Docket No, PATENT APPLICATION 080374.0009

BACKGROUND OF THE INVENTION
[0002] The input stage of the low noise amplifier sets the limits on the sensitivity of the receiver. Therefore, low-noise is one of its most important design goals. Unfortunately, the lower intrinsic gain of transistors at higher frequencies makes it more difficult to achieve a low noise figure at very high frequencies. In such applications, additional noise sources such as gate-induced noise become more prominent with increasing frequency. The low noise amplifier also needs to achieve a sufficient gain to suppress the noise of the following stages and good linearity to handle out-of-band interference while providing a well-defined real impedance, which is normally 50-Ω.
[0003] In order to reduce the effect of noise at high frequency, a common-source stage with inductive degeneration has been used in CMOS low noise amplifier ("LNA") implementations. It can be shown that for an input-matched common-source LNA, the minimum achievable noise factor, Fmin, and the effective transconductance, Gm, are linearly related to the working frequency, ω, 0 I and its inverse, 1/ c ,o respectively. Although this common-source topology is well suited for applications at operating frequencies in the low GHz range, its performance degrades substantially at higher frequencies when ω0 becomes comparable to ωτ.
[0004] In contrast, in a common-gate (CG) LNA, the gate-source and gate-drain parasitic capacitances of the transistor are absorbed into the LC tank and resonated out at the operating frequency. Therefore, to the first order, the noise and gain performance of the common-gate stage is independent of the operating frequency, which is a desirable feature for high frequency design. However, due to the constraints of input matching, it can be shown that the noise factor of a

080374.0009 WEST 5390628 vl 2 Attorney Docket No. PATENT APPLICATION 080374.0009

common-gate LNA has a lower bound of 1+γ for perfect input match, where γ is the channel thermal noise coefficient. This represents a practical limit for noise reduction that restricts high-frequency applications.

080374.0009 WEST 5390628 vl Attorney Docket No. PATENT APPLICATION 080374.0009

SUMMARY OF THE INVENTION
[0005] In accordance with the present invention,, a common-gate low noise amplifier with resistive feed-through is provided that overcomes known problems with high frequency amplifiers.
[0006] In particular, a common-gate low noise amplifier with resistive feed-through is provided that reduces noise effects while maintaining a well-matched input, and that is suitable for applications at either low frequencies or high frequencies.
[0007] In accordance with an exemplary embodiment of the present invention, a radio-frequency amplifier is provided. The radio-frequency amplifier includes a transistor having an input terminal, an output terminal, a control terminal, and a transconductance gm. A series-connected feed-through resistance Rf and feed-through capacitance Cf is connected in parallel with the input terminal and the output terminal of the transistor. A load resistance RL is connected to the output terminal. The control terminal of the transistor is biased at a fixed voltage, such as ac ground. Part of the transistor noise follows the looped path through the feed-through resistor instead of passing on to the load, which reduces the noise figure of the amplifier. In addition, the values of gm, Rf and RL keep the input impedance of a amplifier matched to a well-defined signal source impedance.
[0008] The present invention provides many important technical advantages. One important technical advantage of the present invention is a high-frequency amplifier with improved noise performance that allows radio-frequency signals to be amplified above 20 GHz without the introduction of significant amounts of noise.

080374.0009 WEST 5390628 vl Attorney Docket No, PATENT APPLICATION 080374.0009

[0009] Those skilled in the art will further appreciate the advantages and superior features of the invention together with other important aspects thereof on reading the detailed description that follows in conjunction with the drawings.

080374.0009 WEST 5390628 vl Attorney Docket No. PATENT APPLICATION 080374.0009

BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIGURE 1 is a diagram of a common gate LNA with resistive feed-through in accordance with an exemplary embodiment of the present invention;
[0011] FIGURE 2 is a diagram of a common gate LNA with resistive feed-through and a tank circuit in accordance with an exemplary embodiment of the present invention;
[0012] FIGURE 3 is a gain analysis circuit in accordance with an exemplary embodiment of the present invention;
[0013] FIGURE 4 is a small-signal equivalent circuit of a common gate resistive feed-through LNA in accordance with an exemplary embodiment of the present invention;
[0014] FIGURE 5 is a substrate network model for a MOS transistor in accordance with an exemplary embodiment of the present invention;
[0015] FIGURE 6 is a 24-GHz CMOS LNA in accordance with an exemplary embodiment of the present invention;
[0016] FIGURE 7 is a diagram of a mixer in accordance with an exemplary embodiment of the present invention;
[0017] FIGURE 8 is a table presenting measurements from experimental embodiments of an LNA and a mixer;
[0018] FIGURE 9 shows measured input and output reflection coefficients, Sn and S22, for the experimental embodiments of an LNA and a mixer;
[0019] FIGURE 10 shows the measured power gain and extracted voltage gain for the experimental embodiments of an

LNA and a mixer with a 16.9-GHz local oscillator frequency;
[0020] FIGURE 11 shows the measured large-signal nonlinearity for the experimental embodiments of an LNA and a mixer; and
[0021] FIGURE 12 shows the measured noise figure for the experimental embodiments of an LNA and a mixer.

080374.0009 WEST 5390628 vl Attorney Docket No, PATENT APPLICATION 080374.0009

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0022] In the description that follows, like parts are marked throughout the specification and drawings with the same reference numerals, respectively. The drawing figures might not be to scale, and certain components can be shown in generalized or schematic form and identified by commercial designations in the interest of clarity and conciseness.
[0023] FIGURE 1 is a diagram of a common gate LNA 100 with resistive feed-through in accordance with an exemplary embodiment of the present invention. Common gate LNA 100 can be implemented in CMOS or in other suitable manners .
[0024] Common gate LNA 100 includes transistor 102, which can be a CMOS transistor or other suitable devices. Feed-through resistor 104 is provided in parallel with amplifier 102, and a feed-through capacitance 106 is used to isolate dc level. The gate of transistor 102 is biased at a fixed voltage, and an inductor 108 provides a dc current path from the input terminal to ground.
[0025] Feed-through resistor 104 forms a closed loop with the transistor 102 channel thermal noise (or shot noise) source. As such, part of the noise signal follows a looped path through feed-through resistor 104 instead of passing on to the load, which reduces the noise figure of the LNA.
[0026] In operation, common gate LNA 100 with feed-through path formed by resistor 104 and capacitance 106 provides for improved performance degradation at higher frequencies. The output noise power due to the transistor channel noise can be lowered towards 0 by reducing resistor 104. The dc current needs to be increased to maintain the gain and input matching. By this means, the topology shown provides a direct way to trade between power dissipation and the noise figure, such that common gate LNA 100 with a feed-through path provides

080374.0009 WEST 5390628 vl Attorney Docket No. PATENT APPLICATION 080374.0009

improved performance at very high frequencies where the noise figure takes precedence over power dissipation.
[0027] FIGURE 2 is a diagram of a common gate LNA 200 with resistive feed-through and a tank circuit in accordance with an exemplary embodiment of the present invention. As shown, Rs, is the signal source impedance, Cp is a large capacitor for isolating dc level, and RL is the resistive load at the drain of Mi . Inductors LL and Ls resonate at the operating frequency with a capacitive load at the drain and source of Mi, respectively.
[0028] FIGURE 3 is a gain analysis circuit 300 in accordance with an exemplary embodiment of the present invention. The effective transconductance gm equals 1/(2 * Rs) . It should also be noted that gm is independent of Rf for a matched input.
[0029] FIGURE 4 is a small-signal equivalent circuit 400 of a common gate resistive feed-through LNA in accordance with an exemplary embodiment of the present invention. In addition to the major noise sources (represented as in current sources) , gm is the transistor transconductance, gmb is the backgate transconductance, gg is the real part of the gate admittance, is the transistor channel thermal noise source, and i2 is

the induced gate noise source. At low frequency, where
and gg can be neglected, the feedthrough resistor Rf (which is formed by an external parallel resistance Rp in parallel with the drain-to-source resistance rds) creates a positive feedback loop around the amplifier to enhance the input impedance. At resonance frequency, the input impedance seen looking into the source of Mi can be expressed as:

080374.0009 WEST 5390628 vl Attorney Docket No , PATENT APPLICATION 080374 . 0009

Rf + RL
(1)
Zin ~ l + gmRf (l + χ)
where gm is the transistor transconductance and χ is the ratio of the transistor backgate transconductance gmb to gm. If the input is matched, the effective transconductance of the common gate resistive feed-through stage is given by:

1
G m CGRF
2R, (2 :
which indicates that to the first order at the input matching condition, the gain of the common gate resistive feed-through stage is independent of Rf and gm .
[0030] Assuming a matched input and Rs «RLr the output noise power generated by the thermal noise of Rp and RL is negligible compared to that generated by the transistor channel thermal noise, in which case the noise factor can be approximately expressed as:



where a. is the ratio of gm to the channel conductance at zero drain-to-source voltage, gd0.
[0031] Based on the simplifying assumptions that gate noise and gg may be ignored, the noise of the common gate resistive feed-through amplifier approaches OdB by increasing gmr providing a direct way to trade between power and noise while keeping the input matched. However, at high frequencies, additional effects need to be considered, such as that the coupling between channel and gate is due to a distributed RC network, reflected in the real part of the gate admittance, gg. In the pinch-off region, gg is related to operation frequency (ύor gate-source capacitance, Cgs, and g^o through:

080374.0009 WEST 5390628 vl Attorney Docket No , PATENT APPLICATION 080374 . 0009

C gXs ωn
S* = (4)
5g, d0
This conductance has a thermal noise, if associated with it, which is called induced gate noise, The power spectral density of i is given by:

«. (5)
Af s
where δ is the gate noise coefficient, and i •n2d and / are partially correlated with a complex correlation coefficient c given by:

ln,gln,d
c =
• 2 -2 (6)
n,g n,d
Taking gg into account, the input impedance of the common gate resistive feed-through stage is revised as:



where η(ωϋ) i.s defined as the ratio between gg and gm



If input is perfectly matched to RΞ, the effective transconductance of the common gate resistive feed-through stage is given by:
1
' m,CGRF 2R, -[l-.?„A>7(α>o)] (9)

which indicates that a large gm and high frequency can degrade the gain. This is because the increase of gm results in a larger gg causing more signal loss through the gate.
[0032] If a matched input is provided and Rs «Rι,r the

080374.0009 WEST 5390628 vl ]_ 0 Attorney Docket No , PATENT APPLICATION 080374 . 0009

following expression defines the value of F:

F, CGRF Λ +δη(ω0)gmRs (10)


where the second term represents the contribution of channel thermal noise and the third term represents the contribution of induced gate noise. At low frequencies, η(ω0)→ 0, and equation (10) reduces' to equation (3) .
[0033] An optimum gm exists for minimum noise figure, i.e.,



And the corresponding minimum F is approximately given by:

F, CGRFMn l + ( i2 :


[0034] Since Rf results in positive feedback in the common gate resistive feed-through stage, stability needs to be addressed. Considering the input transistor with feed-through resistor as a two-port network, Zs and ZL are the load impedance at the two ports, source and drain, respectively. It is a sufficient condition to prevent oscillation that the real part of both impedances seen looking into the ports, Z±n and Zoutr are positive. Re [Zιn] and Re[Zoutl can be expressed as



where Rf = Rp || rds , and equations (13) and (14) indicate that as long as Re [ ZL] and Re [ Zs] are positive, stability of the common gate resistive feed-through stage is provided.
[0035] FIGURE 5 is a substrate network model 500 for a MOS transistor in accordance with an exemplary embodiment of the

080374.0009 WEST 5390628 vl 11 Attorney Docket No. PATENT APPLICATION

080374.0009

present invention. Capacitive coupling between the drain and source through this network adversely affects stability and the noise figure. A shunt inductor Lp in series with a large bypass capacitor Cp resonates the equivalent capacitance between drain and source so that the substrate effects are reduced. The series resistance of Lp can be converted to an equivalent parallel resistance, which affects the performance of the LNA as a feed-through resistor. In this case, the feed- through resistance can be expressed as
Rf = Qθ),Lp \\ rds (15)
where RLp is the series resistance of Lp.
[0036] FIGURE 6 is a 24-GHz CMOS LNA 600 in accordance with an exemplary embodiment of the present invention. An experimental embodiment of LNA 600 was also constructed, and T test results from tests performed on that experimental embodiment are discussed herein in greater detail.
[0037] LNA 600 includes three stages. The first stage employs a common-gate with resistive feed-through topology, where shunt inductor L resonates the capacitive coupling between the drain and the source of Mi, while its parasitic resistance RL2 introduces a feed-through resistance described by equation (15). A large capacitor C2 isolates the dc level of the source and the drain. The second and third stages are both common-source with inductive degeneration amplifiers, which are used to enhance the overall gain.
[0038] The peak fτ of the 0.18-μm CMOS device used at 1.5 V bias is about 60 GHz. To achieve the minimum noise figure at 24 GHz, the optimum gmι is estimated to be about 80 mS in accordance with equation (11) . To reduce the power consumption, gml is set to 40 mS. - Vt ) is also lowered by a factor of two from its value of peak fτ, which is a power

080374.0009 WEST 5390628 vl ]_ 2 Attorney Docket No. PATENT APPLICATION 080374.0009

efficient way for reducing current consumption by more than 50%, while reducing fτ by about 10% only. Finally 2 is biased at 8mA with 54 GHz fτ. The second and third stages consume 4mA each.
[0039] Since the feed-through resistor is replaced by an inductor in the first stage, the stability of the amplifier needs to be reexamined. Computer circuit simulations show that the first stage is stable up to 43 GHz. Above 43 GHz, the stability factor of the stage, Kf, is less than one. However, the input impedance of the second stage is located in the stable region with sufficient margin for stable operation in the frequency range of interest.
[0040] FIGURE 7 is a diagram of a mixer 700 in accordance with an exemplary embodiment of the present invention. A conventional single-balanced Gilbert cell is used, and the RF input is applied at the gate of M4 which is used as a transconductance amplifier. The linearity of this transconductance amplifier is improved by using source degeneration inductor s, which also adjusts the input impedance seen looking into the gate of M4 in order to improve the power matching at the LNA-mixer interface. M4 is biased at 4mA dc current.
[0041] The chopping function of mixer 700 is accomplished by the M2~M3 mixing cell and a 1.6 V peak-to-peak differential LO signal is applied. Cascode amplifiers following the differential mixing cell are used to drive the 50-Ω loads. The output-match is accomplished by the LC impedance transforming network.
[0042] FIGURE 8 is a table 800 presenting measurements from experimental embodiments of LNA 600 and mixer 700. The circuits were designed and fabricated using 0.18-μm CMOS transistors. The process used to fabricate the experimental

080374.0009 WEST 5390628 vl 3 Attorney Docket No. PATENT APPLICATION 080374.0009

embodiments used six metal layers with two top layers of 1-μm thick copper. The inductors L and L6 of LNA 600 and L8 of mixer 700 were implemented as slab inductors, and the remaining inductors were implemented as spirals. Shielded pads were employed at both transmission frequency and intermediate frequency ports. Grounded metal underneath the pads prevented loss of the signal power and noise generation associated with substrate resistance.
[0043] Ground rings were placed around each transistor at a minimum distance to reduce the substrate loss. Separated Vdd pads were assigned to LNA 600, mixer 700, and bias circuits. Large on-chip bypass capacitors were placed between each Vdd and ground. The size of the chip was 0.8 x 0.9 mm including a large area occupied by the wide ground rings and pads. The size of the core cell was only 0.4 x 0.5 mm.
[0044] The image rejection of the front-end was -31 dB. This performance was achieved via the large intermediate frequency and the multi-stage nature of LNA 600. The overall current consumption of the front-end was 43 mA, out of which the output buffers consumed 23 mA. The experimental embodiments of LNA 600 and mixer 700 drew 16mA and 4mA, respectively, from a 1.5-V supply voltage.
[0045] FIGURE 9 shows the measured input and output reflection coefficients, Sn and S2 , for the experimental embodiments of LNA 600 and mixer 700. As shown by these measurements, the radio frequency input and the intermediate frequency output are well matched at the respective frequencies .
[0046] FIGURE 10 shows the measured power gain and extracted voltage gain for the experimental embodiments of LNA 600 and mixer 700 with a 16.9-GHz local oscillator frequency. The measurement shows that a 27.5 dB maximum power gain

080374.0009 WEST 5390628 vl 14 Attorney Docket No. PATENT APPLICATION 080374.0009

appears for a transmission frequency of 21.8 GHz and an intermediate frequency of 4.9 GHz. The frequency offset from the 24 GHz is likely due to inaccurate modeling of the MOS transistor and the planar inductor at high frequencies. The experimental embodiment of LNA 600 achieved a 15-dB power gain. The experimental embodiment of mixer 700 further enhanced the signal power by 13 dB. Because of the imperfect conjugate-matching at the LNA-mixer interface, the overall power gain of the front-end was slightly lower than the sum of the individual power gain of the two blocks.
[0047] FIGURE 11 shows the measured large-signal nonlinearity for the experimental embodiments of LNA 600 and mixer 700. The input referred ldB compression points appears at -23dBm.
[0048] FIGURE 12 shows the measured noise figure for the experimental embodiments of LNA 600 and mixer 700. A minimum noise figure of 7.7 dB was achieved for the combined LNA 600 and mixer 700 at 22.08 GHz. The individual noise figures of LNA 600 and mixer 700 were 6 dB and 17.5 dB, respectively. The noise figure of the first common gate resistive feed-through stage was extracted to be 4.8 dB. Applying equation

(3) predicts the ifd only -noise figure of the first stage to be

3.3dB. Applying equation (10) adjusts the prediction of the noise figure to be 4.1 dB by taking gg and if into account, and the remaining amount of 0.7 dB is due to the thermal noise of the parasitic resistance and substrate noise.
[0049] Although exemplary embodiments of a system and method of the present invention have been described in detail herein, those skilled in the art will also recognize that various substitutions and modifications can be made to the systems and methods without departing from the scope and

080374.0009 WEST 5390628 vl 15 Attorney Docket No, PATENT APPLICATION 080374.0009

spirit of the appended claims,

080374.0009 WEST 5390628 vl 16