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1. WO2019222232 - PROCÉDÉ DE CRÉATION D'UN TROU D'INTERCONNEXION ENTIÈREMENT AUTO-ALIGNÉ

Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

[ EN ]

A METHOD FOR CREATING A FULLY SELF-ALIGNED VIA

TECHNICAL FIELD

[0001] Embodiments of the present disclosure pertain to the field of electronic device manufacturing, and in particular, to an integrated circuit (IC) manufacturing. More particularly, embodiments of the disclosure are directed to methods of vias or contacts which skip a layer.

BACKGROUND

[0002] Generally, an integrated circuit (IC) refers to a set of electronic devices, e.g., transistors formed on a small chip of semiconductor material, typically, silicon. Typically, the IC includes one or more layers of metallization having metal lines to connect the electronic devices of the IC to one another and to external connections. Typically, layers of the interlayer dielectric material arc placed between the metallization layers of the IC for insulation.

[0003] As the size of the IC decreases, the spacing between the metal lines decreases. Typically, to manufacture an interconnect structure, a planar process is used that involves aligning and connecting one layer of metallization to another layer of metallization.

[0004] Typically, patterning of the metal lines in the metallization layer is performed independently from the vias above that metallization layer. Conventional via manufacturing techniques, however, cannot provide the full via self-alignment. In the conventional techniques, the vias formed to connect lines in an upper metallization layer to a lower metallization are often misaligned to the lines in the lower metallization layer. The via-line misalignment increases via resistance and leads to potential shorting to the wrong metal line. The via-line misalignment causes device failures, decreases yield, and increases manufacturing cost. Additionally, the conventional methods require high aspect ratio etch, which leads to limited performance and throughput, and the conventional methods can cause damage to the dielectric materials. Thus, there is a need for a method of making a via and/or via pillar that causes no damage to the dielectric material(s) and does not need a high aspect ratio dielectric etch.

SUMMARY

[0005] Apparatuses and methods to provide a fully self-aligned via are described. In one embodiment, an electronic device comprises a first insulating layer. A first metallization layer comprises a set of first conductive lines extending along a first direction, each of the first conductive lines separated from adjacent first conductive lines by the first insulating layer. A second insulating layer is on the first insulating layer. A second metallization layer is on the second insulating layer and comprises a set of second conductive lines. The set of second conductive lines extends along a second direction that crosses the first direction at an angle. A third insulating layer is above the second metallization layer. A third metallization layer is on the third insulating layer and comprises a set of third conductive lines. The set of third conductive lines extends along the first direction and is aligned with the set of first conductive lines. A bridging via is located between the first metallization layer and the third metallization layer. The bridging via does not contact the second metallization layer.

[0006] One or more embodiments are directed to methods to provide a fully self-aligned via. A substrate is provided which comprises a first insulating layer that has a plurality of parallel recessed first conductive lines extending in a first direction. The recessed first conductive lines have a top surface recessed below a top surface of the first insulating layer. First pillars are formed on the recessed first conductive lines. The first pillars extend orthogonal to the top surface of the first insulating layer. A second insulating layer is deposited around the first pillars and on the top surface of the first insulating layer. At least one of the first pillars are selectively removed to form at least one opening in the second insulating layer. A least one first pillar is left on the recessed first conductive lines. A second conductive material is deposited in the at least one opening to form a first via and second conductive lines. The first via connects the first conductive lines to the second conductive lines. The at least one first pillar left on the recessed first conductive lines is removed to form at least one bridging opening in the second insulating layer. At least one bridging pillar is formed on the recessed first conductive lines through the bridging opening. The at least one bridging pillar extends orthogonally to a top surface of the second insulating layer. A third insulating layer is deposited around the at least one bridging pillar and on a portion of the second insulating layer. The at least one bridging pillar is removed to form at least one bridging opening in the second insulating layer and third insulating layer. A third conductive material is deposited in the at least one bridging opening to form a bridging via and third

conductive lines. The bridging via connects the first conductive lines to the third conductive lines.

[0007] In one embodiment, a method to provide a via is described. A substrate is provided that comprises a first insulating layer having a plurality of parallel recessed first conductive lines extending in a first direction. The recessed first conductive lines have a top surface recessed below a top surface of the first insulating layer. The first insulating layer comprises ultra low-^, and the first conductive lines comprising copper or cobalt. A first pillar metal film comprising tungsten is formed on the recessed first conductive lines, and first pillars comprising tungsten oxide are grown from the first pillar metal film on the recessed first conductive lines. The first pillars extend orthogonally to the top surface of the first insulating layer. A second insulating layer is deposited on the first insulating material, around the first pillars and on a top of the at least one first pillar to form an overburden of the second insulating layer. The second insulating layer comprises a flowable silicon oxide. The second insulating layer is planarized to remove the overburden of the second insulating layer and expose the top of the at least one first pillar. A hardmask is formed on the second insulating layer, the hardmask having an opening over at least one first pillar. The at least one first pillar is removed to form the at least one opening in the second insulating layer. At least one first pillar is left on the recessed first conductive lines. A second conductive material is deposited in the at least one opening to form a first via and second conductive lines. The first via connects the first conductive lines to the second conductive lines. The at least one first pillar left on the recessed first conductive lines is removed to form at least one bridging opening in the second insulating layer. A bridging pillar metal film comprising tungsten is formed on the recessed first conductive lines through the bridging opening. At least one bridging pillar comprising tungsten oxide is grown from the bridging pillar metal film. The at least one bridging pillar extends orthogonally to a top surface of the second insulating layer. A third insulating layer is deposited around the at least one bridging pillar and on a portion of the second insulating layer. The third insulating layer is selected from the group consisting of oxides, carbon doped oxides, porous silicon dioxide, carbides, oxycarbides, nitrides, oxynitrides, oxycarbonitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), or any combinations thereof. The at least one bridging pillar is removed to form at least one bridging opening in the second insulating layer and third insulating layer. A third conductive material comprising copper or cobalt is deposited in the at least one bridging opening to form a bridging via and third conductive lines. The bridging via connects the first conductive lines to the third conductive lines.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. The embodiments as described herein are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

[0009] FIG. 1A illustrates a cross-sectional view of an electronic device structure to provide a fully self-aligned via according to one embodiment;

[0010] FIG.1B illustrates a top view of the electronic device structure depicted in FIG.1A;

[0011] FIG. 1C illustrates a perspective view of the electronic device structure depicted in FIG.1A;

[0012] FIG. 2A is a view similar to FIG. 1A, after the conductive lines are recessed according to one embodiment;

[0013] FIG.2B illustrates a top view of the electronic device structure depicted in FIG.2A;

[0014] FIG. 2C illustrates a perspective view of the electronic device structure depicted in FIG.2A;

[0015] FIG. 2D illustrates a view similar to FIG 2A, after a liner has been deposited on recessed conductive lines according to an alternative embodiment;

[0016] FIG. 3A is a view similar to FIG. 2A after a metal film has been deposited on recessed conductive lines according to one embodiment;

[0017] FIG.3B illustrates a top view of the electronic device structure depicted in FIG.3A;

[0018] FIG. 3C illustrates a perspective view of the electronic device structure depicted in FIG.3A;

[0019] FIG. 4A is a view similar to FIG. 3A after a pillars have been grown on recessed conductive lines according to one embodiment;

[0020] FIG.4B illustrates a top view of the electronic device structure depicted in FIG.4A; [0021] FIG. 4C illustrates a perspective view of the electronic device structure depicted in FIG.4A;

[0022] FIG. 5A is a view similar to FIG. 4A after an insulating layer has been deposited according to one embodiment;

[0023] FIG.5B illustrates a top view of the electronic device structure depicted in FIG.5A;

[0024] FIG. 5C illustrates a perspective view of the electronic device structure depicted in FIG.5A;

[0025] FIG. 6A is a view similar to FIG. 5A after a hard mask layer has been formed according to one embodiment;

[0026] FIG.6B illustrates a top view of the electronic device structure depicted in FIG.6A;

[0027] FIG. 6C illustrates a perspective view of the electronic device structure depicted in FIG.6A;

[0028] FIG. 7A is a view similar to FIG. 6A after the substrate has been etched according to one embodiment;

[0029] FIG.7B illustrates a top view of the electronic device structure depicted in FIG.7A;

[0030] FIG. 7C illustrates a perspective view of the electronic device structure depicted in FIG.7A;

[0031] FIG. 8A is a view similar to FIG. 7A after a via has been filled according to one embodiment;

[0032] FIG.8B illustrates a top view of the electronic device structure depicted in FIG.8A;

[0033] FIG. 8C illustrates a perspective view of the electronic device structure depicted in FIG.8A;

[0034] FIG. 9A is a view similar to FIG. 8A after a hard mask has been removed according to one embodiment;

[0035] FIG.9B illustrates a top view of the electronic device structure depicted in FIG.9A;

[0036] FIG. 9C illustrates a perspective view of the electronic device structure depicted in FIG.9A;

[0037] FIG. 10A is a view similar to FIG. 9A after a pillar has been removed according to one embodiment;

[0038] FIG. 10B illustrates a top view of the electronic device structure depicted in FIG. 10A;

[0039] FIG. 10C illustrates a perspective view of the electronic device structure depicted in FIG.10A;

[0040] FIG. 11A is a view similar to FIG. 10A after a metal film has been deposited according to one embodiment;

[0041] FIG. 11B illustrates a top view of the electronic device structure depicted in FIG. 11A;

[0042] FIG. 11C illustrates a perspective view of the electronic device structure depicted in FIG.11A;

[0043] FIG. 12A is a view similar to FIG. 11A after pillars are grown according to one embodiment;

[0044] FIG. 12B illustrates a top view of the electronic device structure depicted in FIG. 12A;

[0045] FIG. 12C illustrates a perspective view of the electronic device structure depicted in FIG.12A;

[0046] FIG. 13A is a view similar to FIG. 12A after an insulating layer has been deposited according to one embodiment;

[0047] FIG. 13B illustrates a top view of the electronic device structure depicted in FIG. 13A;

[0048] FIG. 13C illustrates a perspective view of the electronic device structure depicted in FIG.13A;

[0049] FIG. 14A is a view similar to FIG. 13A after hard mask has been deposited according to one embodiment;

[0050] FIG. 14B illustrates a top view of the electronic device structure depicted in FIG. 14A;

[0051] FIG. 14C illustrates a perspective view of the electronic device structure depicted in FIG.14A;

[0052] FIG. 15A is a view similar to FIG.14A after the substrate has been etched according to one embodiment;

[0053] FIG. 15B illustrates a top view of the electronic device structure depicted in FIG. 15A;

[0054] FIG. 15C illustrates a perspective view of the electronic device structure depicted in FIG.15A;

[0055] FIG. 16A is a view similar to FIG. 15A after bridging via has been filled according to one embodiment;

[0056] FIG. 16B illustrates a top view of the electronic device structure depicted in FIG. 16A;

[0057] FIG. 16C illustrates a perspective view of the electronic device structure depicted in FIG.16A;

[0058] FIG. 17A is a view similar to FIG. 16A after the hard mask has been removed according to one embodiment;

[0059] FIG. 17B illustrates a top view of the electronic device structure depicted in FIG. 17A;

[0060] FIG. 17C illustrates a perspective view of the electronic device structure depicted in FIG.17A;

[0061] FIG. 18A is a view similar to FIG. 17A after conductive lines have been connected according to one embodiment;

[0062] FIG. 18B illustrates a top view of the electronic device structure depicted in FIG. 18A; and

[0063] FIG. 18C illustrates a perspective view of the electronic device structure depicted in FIG.18A;

DETAILED DESCRIPTION

[0064] Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.

[0065] A "substrate" as used herein, refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. For example, a substrate surface on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers. Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize,

hydroxylate, anneal and/or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the film processing steps disclosed may also be performed on an under-layer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include such under-layer as the context indicates. Thus for example, where a film/layer or partial film/layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.

[0066] As used in this specification and the appended claims, the terms“precursor”, “reactant”,“reactive gas” and the like are used interchangeably to refer to any gaseous species that can react with the substrate surface.

[0067] Apparatuses and methods to provide a fully self-aligned via are described. In one embodiment, an electronic device comprises a first insulating layer. A first metallization layer comprises a set of first conductive lines extending along a first direction, each of the first conductive lines separated from adjacent first conductive lines by the first insulating layer. A second insulating layer is on the first insulating layer. A second metallization layer is on the second insulating layer and comprises a set of second conductive lines. The set of second conductive lines extends along a second direction that crosses the first direction at an angle. A third insulating layer is above the second metallization layer. A third metallization layer is on the third insulating layer and comprises a set of third conductive lines. The set of third conductive lines extends along the first direction and is aligned with the set of first conductive lines. A bridging via is located between the first metallization layer and the third metallization layer. The bridging via does not contact the second metallization layer.

[0068] In one embodiment, the bridging via is self-aligned along the first direction to one of the second conductive lines.

[0069] In one embodiment, a fully self-aligned via is the bridging via that is self-aligned along at least two directions to the conductive lines in a lower (or first) and an upper (or third) metallization layer. In one embodiment, the fully self-aligned via is defined by a hard mask in one direction and the underlying insulating layer in another direction, as described in further detail below.

[0070] Comparing to the conventional techniques, some embodiments advantageously provide fully self-aligned vias that cause no damage to the dielectric material(s) and does not need a high aspect ratio dielectric etch. In some embodiments, the fully self-aligned vias

provide lower via resistance and capacitance benefits over the conventional vias. Some embodiments of the self-aligned vias provide full alignment between the vias and the conductive lines of the metallization layers that is substantially error free that advantageously increase the device yield and reduce the device cost.

[0071] In the following description, numerous specific details, such as specific materials, chemistries, dimensions of the elements, etc. are set forth in order to provide thorough understanding of one or more of the embodiments of the present disclosure. It will be apparent, however, to one of ordinary skill in the art that the one or more embodiments of the present disclosure may be practiced without these specific details. In other instances, semiconductor fabrication processes, techniques, materials, equipment, etc., have not been descried in great details to avoid unnecessarily obscuring of this description. Those of ordinary skill in the art, with the included description, will be able to implement appropriate functionality without undue experimentation.

[0072] While certain exemplary embodiments of the disclosure are described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current disclosure, and that this disclosure is not restricted to the specific constructions and arrangements shown and described because modifications may occur to those ordinarily skilled in the art.

[0073] Reference throughout the specification to “one embodiment”, “another embodiment”, or“an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in a least one embodiment of the present disclosure. Thus, the appearance of the phrases“in one embodiment” or“in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0074] FIG. 1A illustrates a cross-sectional view 100 of an electronic device structure to provide a fully self-aligned via according to one embodiment. FIG.1B is a top view 110 of the electronic device depicted in FIG. 1A, and FIG. 1C is a perspective view 120 of the electronic device depicted in FIG. 1A. A lower metallization layer (Mx) comprises a set of conductive lines 103 that extend along an X axis (direction) 121 on an insulating layer 102 on a substrate 101. The X axis of FIGS. 1A-1C extends orthogonally to the plane of the Figure page. As shown in FIGS. 1A-1C, X axis (direction) 121 crosses Y axis (direction) 122 at an angle 123.

In one embodiment, angle 123 is about 90 degrees. In another embodiment, angle 123 is an angle that is other than the 90 degrees angle. The insulating layer 102 comprises trenches 104. The conductive lines 103 are deposited in trenches 104.

[0075] In an embodiment, the substrate 101 comprises a semiconductor material, e.g., silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), aluminum indium arsenide (InAlAs), other semiconductor material, or any combination thereof. In an embodiment, substrate 101 is a semiconductor-on-isolator (SOI) substrate including a bulk lower substrate, a middle insulation layer, and a top monocrystalline layer. The top monocrystalline layer may comprise any material listed above, e.g., silicon. In various embodiments, the substrate 101 can be, e.g., an organic, a ceramic, a glass, or a semiconductor substrate. Although a few examples of materials from which the substrate 101 may be formed are described here, any material that may serve as a foundation upon which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) may be built falls within the spirit and scope of the present disclosure.

[0076] In one embodiment, substrate 101 includes one or more metallization interconnect layers for integrated circuits. In at least some embodiments, the substrate 101 includes interconnects, for example, vias, configured to connect the metallization layers. In at least some embodiments, the substrate 101 includes electronic devices, e.g., transistors, memories, capacitors, resistors, optoelectronic devices, switches, and any other active and passive electronic devices that are separated by an electrically insulating layer, for example, an interlayer dielectric, a trench insulation layer, or any other insulating layer known to one of ordinary skill in the art of the electronic device manufacturing. In one embodiment, the substrate 101 includes one or more layers above substrate 101 to confine lattice dislocations and defects.

[0077] Insulating layer 102 can be any material suitable to insulate adjacent devices and prevent leakage. In one embodiment, electrically insulating layer 102 is an oxide layer, e.g., silicon dioxide, or any other electrically insulating layer determined by an electronic device design. In one embodiment, insulating layer 102 comprises an interlayer dielectric (ILD). In one embodiment, insulating layer 102 is a low-k dielectric that includes, but is not limited to, materials such as, e.g., silicon dioxide, silicon oxide, carbon doped oxide (“CDO”), e.g.,

carbon doped silicon dioxide, porous silicon dioxide (SiO2), silicon nitride (SiN), or any combination thereof.

[0078] In one embodiment, insulating layer 102 includes a dielectric material having a k-value less than 5. In one embodiment, insulating layer 102 includes a dielectric material having a k-value less than 2. In at least some embodiments, insulating layer 102 includes oxides, carbon doped oxides, porous silicon dioxide, carbides, oxycarbides, nitrides, oxynitrides, oxycarbonitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), or any combinations thereof, other electrically insulating layer determined by an electronic device design, or any combination thereof. In at least some embodiments, insulating layer 102 may include polyimide, epoxy, photodefinable materials, such as benzocyclobutene (BCB), and WPR-series materials, or spin-on-glass.

[0079] In one embodiment, insulating layer 102 is a low-k interlayer dielectric to isolate one metal line from other metal lines on substrate 101. In one embodiment, the thickness of the insulating layer 102 is in an approximate range from about 10 nanometers (nm) to about 2 microns (µm).

[0080] In an embodiment, insulating layer 102 is deposited using one of deposition techniques, such as but not limited to a chemical vapor deposition (“CVD”), a physical vapor deposition (“PVD”), molecular beam epitaxy (“MBE”), metalorganic chemical vapor deposition (“MOCVD”), atomic layer deposition (“ALD”), spin-on, or other insulating deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

[0081] In one embodiment, the lower metallization layer Mx comprising conductive lines 103 (i.e., metal lines) is a part of a back end metallization of the electronic device. In one embodiment, the insulating layer 102 is patterned and etched using a hard mask to form trenches 104 using one or more patterning and etching techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the size of trenches 104 in the insulating layer 102 is determined by the size of conductive lines formed later on in a process.

[0082] In one embodiment, forming the conductive lines 103 involves filling the trenches 104 with a layer of conductive material. In one embodiment, a base layer (not shown) is first deposited on the internal sidewalls and bottom of the trenches 104, and then the conductive layer is deposited on the base layer. In one embodiment, the base layer includes a conductive seed layer (not shown) deposited on a conductive barrier layer (not shown). The seed layer can include copper (Cu), and the conductive barrier layer can include aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), and the like metals. The conductive barrier layer can be used to prevent diffusion of the conductive material from the seed layer, e.g., copper or cobalt, into the insulating layer 102. Additionally, the conductive barrier layer can be used to provide adhesion for the seed layer (e.g., copper).

[0083] In one embodiment, to form the base layer, the conductive barrier layer is deposited onto the sidewalls and bottom of the trenches 104, and then the seed layer is deposited on the conductive barrier layer. In another embodiment, the conductive base layer includes the seed layer that is directly deposited onto the sidewalls and bottom of the trenches 104. Each of the conductive barrier layer and seed layer may be deposited using any think film deposition technique known to one of ordinary skill in the art of semiconductor manufacturing, e.g., sputtering, blanket deposition, and the like. In one embodiment, each of the conductive barrier layer and the seed layer has the thickness in an approximate range from about 1 nm to about 100 nm. In one embodiment, the barrier layer may be a thin dielectric that has been etched to establish conductivity to the metal layer below. In one embodiment, the barrier layer may be omitted altogether and appropriate doping of the copper line may be used to make a“self-forming barrier”.

[0084] In one embodiment, the conductive layer e.g., copper or cobalt, is deposited onto the seed layer of base layer of copper, by an electroplating process. In one embodiment, the conductive layer is deposited into the trenches 104 using a damascene process known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the conductive layer is deposited onto the seed layer in the trenches 104 using a selective deposition technique, such as but not limited to electroplating, electrolysis, CVD, PVD, MBE, MOCVD, ALD, spin-on, or other deposition techniques know to one of ordinary skill in the art of microelectronic device manufacturing.

[0085] In one embodiment, the choice of a material for conductive layer for the conductive lines 103 determines the choice of a material for the seed layer. For example, if the material for the conductive lines 103 includes copper, the material for the seed layer also includes copper. In one embodiment, the conductive lines 103 include a metal, for example, copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), vanadium (V),

molybdenum (Mo), palladium (Pd), gold (Au), silver (Ag), platinum (Pt), indium (In), tin (Sn), lead (Pd), antimony (Sb), bismuth (Bi), zinc (Zn), cadmium (Cd), or any combination thereof.

[0086] In one embodiment, portions of the conductive layer and the base layer are removed to even out top portions of the conductive lines 103 with top portions of the insulating layer 102 using a chemical-mechanical polishing (“CMP”) technique known to one of ordinary skill in the art of microelectronic device manufacturing.

[0087] In one non-limiting example, the thickness (as measured along the z-axis of FIGS. 1A-1C) of the conductive lines 103 is in an approximate range from about 15 nm to about 1000 nm. In one non-limiting example, the thickness of the conductive lines 103 is from about 20 nm to about 200 nm. In one non-limiting example, the width (as measured along the y-axis of FIGS.1A-1C) of the conductive lines 103 is in an approximate range from about 5 nm to about 500 nm. In one non-limiting example, the spacing (pitch) between the conductive lines 103 is from about 2 nm to about 500 nm. In more specific non-limiting example, the spacing (pitch) between the conductive lines 103 is from about 5nm to about 50 nm.

[0088] In an embodiment, the lower metallization layer Mx is configured to connect to other metallization layers (not shown). In an embodiment, the metallization layer Mx is configured to provide electrical contact to electronic devices, e.g., transistor, memories, capacitors, resistors, optoelectronic devices, switches, and any other active and passive electronic devices that are separated by an electrically insulating layer, for example, an interlayer dielectric, a trench insulation layer, or any other insulating layer known to one of ordinary skill in the art of electronic device manufacturing.

[0089] FIG. 2A is a view 200 similar to cross-sectional view 100 of FIG. 1A, after the conductive lines 103 are recessed according to one embodiment. FIG. 2B is a top view 210 of the electronic device depicted in FIG. 2A, and FIG. 2C is a perspective view 220 of the electronic device depicted in FIG. 2A. The conductive lines 103 are recessed to a predetermined depth to form recessed conductive lines 201. As shown in FIGS. 2A-2C, trenches 205 are formed in the insulating layer 102. Each trench 204 has sidewalls 204 that are portions of insulating layer 102 and a bottom that is a top surface 203 of the recessed conductive lines 201.

[0090] In one embodiment, the depth of the trenches 205 is from about 10 nm to about 500 nm. In one embodiment, the depth of the trenches 205 is from about 10% to about 100% of the thickness of the recessed conductive lines 201. In one embodiment, the conductive lines 103 are recessed using one or more of wet etching, dry etching, or a combination thereof techniques known to one of ordinary skill in the art of electronic device manufacturing.

[0091] FIG. 2D is a view 220a similar to FIG. 2A, after a liner 207 is deposited on the recessed conductive lines 201 according to one embodiment. In some embodiments, the liner 207 is deposited on the sidewalls 204 of the trenches 205.

[0092] In one embodiment, liner 207 is deposited to protect the recessed conductive lines 201 from changing properties later on in a process (e.g., during tungsten deposition, or other processes). In one embodiment, liner 207 is a conductive liner. In another embodiment, liner 207 is a non-conductive liner. In one embodiment, when liner 207 is a non-conductive liner, the liner 207 is removed later on in a process, as known to those of skill in the art. In one embodiment, liner 207 includes titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), or any combination thereof. In another embodiment, liner 207 is an oxide, e.g., aluminum oxide (Al2O3), titanium oxide (TiO2). In yet another embodiment, liner 207 is a nitride, e.g., silicon nitride (SiN). In an embodiment, the liner 207 is deposited to the thickness from about 0.5 nm to about 10 nm.

[0093] In an embodiment, the liner 207 is deposited using an atomic layer deposition (ALD) technique. In one embodiment, the liner 207 is deposited using one of deposition techniques, such as but not limited to a CVD, PVD, MBE, MOCVD, spin-on, or other liner deposition techniques know to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the liner 207 may be selectively removed using one or more of the dry and wet etching techniques known to one of ordinary skill in the art of electronic device manufacturing.

[0094] While a liner may be present in one or more of the foregoing embodiments, for ease of drawing, the liner has been omitted from the figures.

[0095] FIG. 3A is a view 300 similar to FIG. 2A, after a gapfill layer 301 is deposited on the recessed conductive lines 201, and a portion of the insulating layer 102 according to one embodiment. FIG.3B is a top view 310 of the electronic device depicted in FIG.3A, and FIG. 3C is a perspective view 320 of the electronic device depicted in FIG.3A. As shown in FIGS. 3A-3C, gapfill layer 301 is deposited on the top surface 203 of the recessed conductive lines 201, the sidewalls 204 of the trenches 205 and top portions of the insulating layer 102. In one embodiment, gapfill layer 301 is a tungsten (W) layer, or other gapfill layer to provide selective growth pillars. In some embodiments, gapfill layer 301 is a metal film or a metal

containing film. Suitable metal films include, but are not limited to, films including one or more of cobalt (Co), molybdenum (Mo), tungsten (W), tantalum (Ta), titanium (Ti), ruthenium (Ru), rhodium (Rh), copper (Cu), iron (Fe), manganese (Mn), vanadium (V), niobium (Nb), hafnium (Hf), zirconium (Zr), yttrium (Y), aluminum (Al), tin (Sn), chromium (Cr), lanthanum (La), or any combination thereof. In some embodiments, seed gapfill layer 301 comprises is a tungsten (W) seed gapfill layer.

[0096] In one embodiment, the gapfill layer 301 is deposited using one of deposition techniques, such as but not limited to an ALD, a CVD, PVD, MBE, MOCVD, spin-on or other liner deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

[0097] In some embodiments, deposition of the gapfill layer 301 includes formation of a seed gapfill layer (not shown). As will be understood by the skilled artisan, a seed gapfill layer is a relatively thin layer of material that can increase the nucleation rate (i.e., growth rate) of the gapfill layer 301. In some embodiments, the seed gapfill layer is the same material as the gapfill layer 301 deposited by a different technique. In some embodiments, the seed gapfill layer is a different material than the gapfill layer 301.

[0098] The formation of the gapfill layer 301 may be described as using a bulk deposition of the gapfill material to form an overburden (not illustrate) on the top of the substrate followed by planarization to remove the overburden. In some embodiments, the gapfill layer 301 is formed by a selective deposition process that forms substantially no (e.g., <5% area) overburden on the insulating layer 102.

[0099] Portions of the seed gapfill layer 301 may then be removed to expose top portions of the insulating layer 102 according to one embodiment, and as illustrated in FIGS. 3A-3C. In one embodiment, the portions of the seed gapfill layer 301 are removed using one of the chemical-mechanical planarization (CMP) techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

[00100] FIG. 4A is a view 400 similar to FIG. 3A, after self-aligned selective growth pillars 401 are formed using the seed gapfill layer 301 according to one embodiment. FIG.4B is a top view 410 of the electronic device depicted in FIG. 4A, and FIG. 4C is a perspective view 420 of the electronic device depicted in FIG. 4A. As shown in FIGS. 4A-4C, an array of the self-aligned selective growth pillars 401 has the same pattern as the set of the recessed conductive lines 201. As shown in FIGS. 4A-4C, the pillars 401 extend substantially orthogonally from

the top surfaces of the recessed conductive lines 201. As shown in FIGS. 4A-4C, the pillars 401 extend along the same direction as the recessed conductive lines 201. As shown in FIGS. 4A-4C, the pillars are separated by gaps 402.

[00101] Referring to FIGS. 4A-4C, in one embodiment, the pillars 401 are selectively grown from the gapfill layer 301 on portions of the insulating layer 102 and on the recessed conductive lines 201. In one embodiment, portions of the gapfill layer 301 above the recessed conductive lines 201 are expanded for example, by oxidation, nitridation, or other process to grow pillars 401. In one embodiment, the gapfill layer 301 is oxidized by exposure to an oxidizing agent or oxidizing conditions to transform the metal or metal containing gapfill layer 301 to metal oxide pillars 401. In one embodiment, pillars 401 include an oxide of one or more metals listed above. In more specific embodiment, pillars 401 include tungsten oxide (e.g., WO, WO3 and other tungsten oxide).

[00102] The oxidizing agent can be any suitable oxidizing agent including, but not limited to, O2, O3, N2O, H2O, H2O2, CO, CO2, N2/Ar, N2/He, N2/Ar/He, ammonium persulphate, organic peroxide agents, such as meta-chloroperbenzoic acid and peracids (e.g. trifluoroperacetic acid, 2,4-dinitroperbenzoic acid, peracetic acid, persulfuric acid, percarbonic acid, perboric acid, and the like), or any combination thereof. In some embodiments, the oxidizing conditions comprise a thermal oxidation, plasma enhanced oxidation, remote plasma oxidation, microwave and radio-frequency oxidation (e.g., inductively coupled plasma (ICP), capacitively coupled plasma (CCP)).

[00103] In one embodiment, the pillars 401 are formed by oxidation of the seed gapfill layer at any suitable temperature depending on, for example, the composition of the seed gapfill layer and the oxidizing agent. In some embodiments, the oxidation occurs at a temperature in an approximate range of about 25 °C to about 800 °C. In some embodiments, the oxidation occurs at a temperature greater than or equal to about 150oC.

[00104] In one embodiment, the height of the pillars 401 is in an approximate range from about 5 angstroms (Å) to about 10 microns (µm).

[00105] FIG. 5A is a view 500 similar to FIG. 4A, and, after an insulating layer 501 is deposited to overfill the gaps 402 between the pillars 401 according to one embodiment. FIG. 5B is a top view 510 of the electronic device depicted in FIG. 5A, and FIG.5C is a perspective view 520 of the electronic device depicted in FIG. 5A. As shown in FIGS. 5A-5C, insulating

layer 501 is deposited on and around the pillars 401 and through the gaps 402 on the portions of the insulating layer 102 between the pillars 401.

[00106] In one embodiment, insulating layer 501 is a low-k gapfill layer. In one embodiment, insulating layer 501 is a flowable silicon oxide (FSiOx) layer. In at least some embodiments, insulating layer 501 is an oxide layer, e.g., silicon dioxide (SiO2), or any other electrically insulating layer determined by an electronic device design. In one embodiment, insulating layer 501 is an interlayer dielectric (ILD). In one embodiment, insulating layer 501 is a low-k dielectric that includes, but is not limited to, materials such as, e.g., silicon dioxide, silicon oxide, a carbon based material, e.g., a porous carbon film, carbon doped oxide (“CDO”), e.g. carbon doped silicon dioxide, porous silicon dioxide, porous silicon oxide carbide hydride (SiOCH), silicon nitride, or any combination thereof. In one embodiment, insulating layer 501 is a dielectric material having k-value less than 3. In more specific embodiment, insulating layer 501 is a dielectric material having k-value in an approximate range from about 2.2 to about 2.7. In one embodiment, insulating layer 501 includes a dielectric material having k-value less than 2. In one embodiment, insulating layer 501 represents one of the insulating layers described above with respect to insulating layer 102.

[00107] In one embodiment, insulating layer 501 is a low-k interlayer dielectric to isolate one metal line from other metal lines. In one embodiment, insulating layer 501 is deposited using one of deposition techniques, such as but not limited to a CVD, spin-on, an ALD, PVD. MBE, MOCVD, or other low-k insulating layer deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

[00108] FIG. 6A is a view 600 after a hard mask layer 602 is deposited on insulating layer 601 according to one embodiment. FIG. 6B is a top view 610 of the electronic device depicted in FIG. 6A, and FIG. 6C is a perspective view 620 of the electronic device depicted in FIG. 6A. In one embodiment, hard mask layer 602 is a metallization layer hard mask. As shown in FIGS. 6A-6C, the hard mask layer 602 is patterned to define a plurality of trenches 603. As shown in FIGS. 6A-6C, the trenches 603 extend along a Y axis (direction) 122 that crosses an X axis (direction) 121 at an angle 123. In one embodiment, Y axis 122 is substantially perpendicular to X axis 121. In one embodiment, patterned hard mask layer 602 is a carbon hard mask layer, a metal oxide hard mask layer, a metal nitride hard mask layer, a silicon nitride hard mask layer, a silicon oxide hard mask layer, a carbide hard mask layer, or other hard mask layer known to one of ordinary skill in the art of microelectronic device

manufacturing. In one embodiment, the patterned hard mask layer 602 is formed using one or more hard mask patterning techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the insulating layer 601 is etched through a patterned hard mask layer to form trenches 603 using one or more of etching techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the size of trenches 603 in the insulating layer 601 is determined by the size of conductive lines formed later on in a process.

[00109] In one embodiment, hard mask layer 602 includes a photoresist layer. In one embodiment, hard mask layer 602 includes one or more hard mask layers. In one embodiment, the insulating layer 601 is a hard mask layer. In one embodiment, insulating layer 601 includes a bottom anti-reflective coating (BARC) layer. In one embodiment, insulating layer 601 includes a titanium nitride (TiN) layer, a tungsten carbide (WC) layer, a tungsten bromide carbide (WBC) layer, a carbon hard mask layer, a metal oxide hard mask layer, a metal nitride hard mask layer, a silicon nitride hard mask layer, a silicon oxide hard mask layer, a carbide hard mask layer, other hard mask layer, or any combination thereof. In one embodiment, insulating layer 601 represents one of the insulating layers described above. In one embodiment, hard mask layer 602 is deposited using one or more mask layer deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, insulating layer 601 is deposited using one of deposition techniques, such as but not limited to a CVD, PVD, MBE, NOCVD, spin-on, or other insulating layer deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the trenches 603 is formed using one or more of the patterning and etching techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

[00110] FIG. 7A is a view 700 similar to FIG. 6A after at least one self-aligned selectively grown pillars 401 is selectively removed to form opening 701 according to one embodiment. FIG. 7B is a top view 710 of the electronic device depicted in FIG. 7A, and FIG. 7C is a perspective view 720 of the electronic device depicted in FIG.7A. As shown in FIGS. 7A-7C, the pillars 401 are removed selectively to the insulating layer 501, insulating layer 102, and recessed conductive lines 201. In another embodiment, when liner 207 is a conductive liner, liner 207 remains in place, and the pillars 401 are removed selectively to the insulating layer 501, insulating layer 102, and liner 207. As shown in FIGS. 7A-7C, opening 701 is formed in the insulating layers 501 and 102. Opening 701 extends along the same axis as the recessed conductive lines 201. As shown in FIGS. 7A-7C, each opening 701 has a bottom that is a top surface 203 of recessed conductive lines 201. If there is a liner 207, the bottom of the opening would be the top surface of liner 207. In an embodiment, liner 207 is not present so that each opening 701 has a bottom that is a top surface of the recessed conductive lines 201 and opposing sidewalls that include portions of insulating layers 501 and 102. Generally, the aspect ratio of the trench refers to the ratio of the depth of the trench to the width of the opening. In one embodiment, the aspect ratio of each opening 701 is in an approximate range from about 1:1 to about 200:1.

[00111] In one embodiment, the pillars 401 are selectively removed using one or more of the dry and wet etching techniques known to one of ordinary skill in the art of electronic device manufacturing. In one embodiment, the pillars 401 are selectively wet etched by e.g., 5 wt.% of ammonium hydroxide (NH4OH) aqueous solution at the temperature of about 80 °C. In one embodiment, hydrogen peroxide (H2O2) is added to the 5 wt. % NH4OH aqueous solution to increase the etching rate of the pillars 401. In one embodiment, the pillars 401 are selectively wet etched using hydrofluoric acid (HF) and nitric acid (HNO3) in a ratio of 1:1. In one embodiment, the pillars 401 are selectively wet etched using HF and HNO3 in a ratio of 3:7 respectively. In one embodiment, the pillars 401 are selectively wet etched using HF and HNO3 in a ratio of 4:1, respectively. In one embodiment, the pillars 401 are selectively wet etched using HF and HNO3 in a ratio of 30%:70%, respectively. In one embodiment, the pillars 401 including tungsten (W), titanium (Ti), or both titanium and tungsten are selectively wet etched using NH4OH and H2O2 in a ratio of 1:2, respectively. In one embodiment, the pillars 401 are selectively wet etched using 305 grams of potassium ferricyanide (K3Fe(CN)6), 44.5 grams of sodium hydroxide (NaOH) and 1000ml of water (H2O). In one embodiment, the pillars 401 are selectively wet etched using diluted or concentrated one or more of the chemistries including hydrochloric acid (HCl), nitric acid (HNO3), sulfuric acid (H2SO4), hydrogen fluoride (HF), and hydrogen peroxide (H2O2). In one or more embodiments, the pillars 401 are selectively etched using a solution of HF and HNO3, a solution of NH4OH and H2O2, WCl5, WF6, niobium fluoride (NbF5), chlorine with a hydrocarbon. In one or more embodiment, the hydrocarbon can be a monocarbon (e.g. CH4) or multicarbon-based hydrocarbon. In one embodiment, the pillars 401 are selectively wet etched using HF, HNO3, and acetic acid (CH3COOH) in a ratio of 4:4:3, respectively. In one embodiment, the pillars 401 are selectively dry etched using a bromotrifluoromethane (CBrF3) reactive ion etching (RIE) technique. In one embodiment, the pillars 401 are selectively dry etched using chlorine-, fluorine-, bromine-, or any combination thereof, based chemistries. In one embodiment, the pillars 401 are selectively wet etched using hot or warm Aqua Regia mixture including HCl and HNO3 in a ratio of 3:1, respectively. In one embodiment, the pillars 401 are selectively etched using alkali with oxidizers (potassium nitrate (KNO3) and lead dioxide (PbO2)).

[00112] FIGS. 7A-7C show views of an embodiment in which at least one of the pillars 401 is removed and at least one of the pillars 401 remains. The skilled artisan will recognize that selective removal of some of the pillars can be effected by any suitable technique including, but not limited to, masking and lithography.

[00113] FIG. 8A is a view 800 that is similar to FIG. 7A after a metallization layer with conductive lines 801 is deposited in the opening 701 on recessed conductive lines 201. FIG. 8B is a top view 810 of the electronic device depicted in FIG. 8A, and FIG.8C is a perspective view 820 of the electronic device depicted in FIG. 8A. Metallization layer with conductive lines 801 comprises a set of conductive lines which extend along a second direction and cross the first direction at an angle. In one or more embodiment, lower metallization layer Mx is connected to metallization layer with conductive lines 801, also known as a middle metallization layer My.

[00114] In one embodiment, forming the conductive lines 801 involves filling the opening 701 with a layer of conductive material. In one embodiment, a base layer (not shown) is first deposited on the internal sidewalls and bottom of the opening 701 onto the recessed conductive lines 201, and then the conductive layer is deposited on the base layer. In one embodiment, the base layer includes a conductive seed layer (not shown) deposited on a conductive barrier layer (not shown). The seed layer can include copper (Cu), and the conductive barrier layer can include aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), and the like metals. The conductive barrier layer can be used to prevent diffusion of the conductive material from the seed layer, e.g., copper or cobalt, into the insulating layer 102. Additionally, the conductive barrier layer can be used to provide adhesion for the seed layer (e.g., copper).

[00115] In one embodiment, to form the base layer, the conductive barrier layer is deposited onto the sidewalls and bottom of the opening 701, and then the seed layer is deposited on the conductive barrier layer. In another embodiment, the conductive base layer includes the seed layer that is directly deposited onto the sidewalls and bottom of the opening 701. Each of the conductive barrier layer and seed layer may be deposited using any think film deposition technique known to one of ordinary skill in the art of semiconductor manufacturing, e.g., sputtering, blanket deposition, and the like. In one embodiment, each of the conductive barrier layer and the seed layer has the thickness in an approximate range from about 1 nm to about 100 nm. In one embodiment, the barrier layer may be a thin dielectric that has been etched to establish conductivity to the metal layer below. In one embodiment, the barrier layer may be omitted altogether and appropriate doping of the copper line may be used to make a“self-forming barrier”.

[00116] In one embodiment, the conductive layer e.g., copper or cobalt, is deposited onto the seed layer of base layer of copper, by an electroplating process. In one embodiment, the conductive layer is deposited into the opening 701 using a damascene process known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the conductive layer is deposited onto the seed layer in the opening 701 using a selective deposition technique, such as but not limited to electroplating, electrolysis, CVD, PVD, MBE, MOCVD, ALD, spin-on, or other deposition techniques know to one of ordinary skill in the art of microelectronic device manufacturing.

[00117] In one embodiment, the choice of a material for conductive layer for the conductive lines 801 determines the choice of a material for the seed layer. For example, if the material for the conductive lines 801 includes copper, the material for the seed layer also includes copper. In one embodiment, the conductive lines 801 include a metal, for example, copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), silver (Ag), platinum (Pt), indium (In), tin (Sn), lead (Pd), antimony (Sb), bismuth (Bi), zinc (Zn), cadmium (Cd), or any combination thereof.

[00118] FIG. 9A is a view 900 similar to FIG. 8A, after portions of the hard mask layer 602, insulating layer 601 and insulating layer 501 are removed to expose a top surface of insulating layer 501 and pillar 401 according to one embodiment. FIG. 9B is a top view 910 of the electronic device depicted in FIG. 9A, and FIG. 9C is a perspective view 920 of the electronic device depicted in FIG.9A.

[00119] FIG. 10A is a view 1000 similar to FIG.9A after at least one self-aligned selectively grown pillar 401 is selectively removed to form opening 1001 according to one embodiment. FIG. 10B is a top view 1010 of the electronic device depicted in FIG. 10A, and FIG. 10C is a perspective view 1020 of the electronic device depicted in FIG. 10A. FIGS. 10A-10C show views of an embodiment in which at least one of the pillars 401 is removed and at least one of the pillars 401 remains. The skilled artisan will recognize that selective removal of some of the pillars can be effected by any suitable technique including, but not limited to, masking and lithography.

[00120] As shown in FIGS. 10A-10C, the pillars 401 are removed selectively to the insulating layer 501, insulating layer 102, and recessed conductive lines 201. As shown in FIGS. 7A-7C, openings 1001 are formed in the insulating layers 501 and 102. Openings 1001 extend along the same axis as the recessed conductive lines 201. As shown in FIGS. 7A-7C, each trench 701 has a bottom that is a top surface 203 of recessed conductive lines 201. Generally, the aspect ratio of the opening refers to the ratio of the depth of the opening to the width of the opening. In one embodiment, the aspect ratio of each opening 1001 is in an approximate range from about 1:1 to about 200:1.

[00121] In one embodiment, the pillars 401 are selectively removed using one or more of the dry and wet etching techniques known to one of ordinary skill in the art of electronic device manufacturing. In one embodiment, the pillars 401 are selectively wet etched by e.g., 5 wt.% of ammonium hydroxide (NH4OH) aqueous solution at the temperature of about 80 °C. In one embodiment, hydrogen peroxide (H2O2) is added to the 5 wt. % NH4OH aqueous solution to increase the etching rate of the pillars 401. In one embodiment, the pillars 401 are selectively wet etched using hydrofluoric acid (HF) and nitric acid (HNO3) in a ratio of 1:1. In one embodiment, the pillars 401 are selectively wet etched using HF and HNO3 in a ratio of 3:7 respectively. In one embodiment, the pillars 401 are selectively wet etched using HF and HNO3 in a ratio of 4:1, respectively. In one embodiment, the pillars 401 are selectively wet etched using HF and HNO3 in a ratio of 30%:70%, respectively. In one embodiment, the pillars 401 including tungsten (W), titanium (Ti), or both titanium and tungsten are selectively wet etched using NH4OH and H2O2 in a ratio of 1:2, respectively. In one embodiment, the pillars 401 are selectively wet etched using 305 grams of potassium ferricyanide (K3Fe(CN)6), 44.5 grams of sodium hydroxide (NaOH) and 1000ml of water (H2O). In one embodiment, the pillars 401 are selectively wet etched using diluted or concentrated one or more of the chemistries including hydrochloric acid (HCl), nitric acid (HNO3), sulfuric acid (H2SO4), hydrogen fluoride (HF), and hydrogen peroxide (H2O2). In one or more embodiments, the pillars 401 are selectively etched using a solution of HF and HNO3, a solution of NH4OH and H2O2, WCl5, WF6, niobium fluoride (NbF5), chlorine with a hydrocarbon. In one or more embodiment, the hydrocarbon can be a monocarbon (e.g. CH4) or multicarbon-based hydrocarbon. In one embodiment, the pillars 401 are selectively wet etched using HF, HNO3, and acetic acid (CH3COOH) in a ratio of 4:4:3, respectively. In one embodiment, the pillars 401 are selectively dry etched using a bromotrifluoromethane (CBrF3) reactive ion etching (RIE) technique. In one embodiment, the pillars 401 are selectively dry etched using chlorine-, fluorine-, bromine-, or any combination thereof, based chemistries. In one embodiment, the pillars 401 are selectively wet etched using hot or warm Aqua Regia mixture including HCl and HNO3 in a ratio of 3:1, respectively. In one embodiment, the pillars 401 are selectively etched using alkali with oxidizers (potassium nitrate (KNO3) and lead dioxide (PbO2)).

[00122] FIG. 11A is a view 1100 similar to FIG. 10A, after a gapfill layer 1101 is deposited on the recessed conductive lines 201, and a portion of the insulating layer 102 and a portion of the insulating layer 501 according to one embodiment. FIG. 11B is a top view 1110 of the electronic device depicted in FIG. 11A, and FIG. 11C is a perspective view 1120 of the electronic device depicted in FIG. 11A. As shown in FIGS. 11A-11C, gapfill layer 1101 is deposited on the top surface 203 of the recessed conductive lines 201, the sidewalls 204 of the opening 1001 and top portions of the insulating layer 102. In one embodiment, gapfill layer 1101 is a tungsten (W) layer, or other gapfill layer to provide selective growth pillars. In some embodiments, gapfill layer 1101 is a metal film or a metal containing film. Suitable metal films include, but are not limited to, films including one or more of cobalt (Co), molybdenum (Mo), tungsten (W), tantalum (Ta), titanium (Ti), ruthenium (Ru), rhodium (Rh), copper (Cu), iron (Fe), manganese (Mn), vanadium (V), niobium (Nb), hafnium (Hf), zirconium (Zr), yttrium (Y), aluminum (Al), tin (Sn), chromium (Cr), lanthanum (La), or any combination thereof. In some embodiments, seed gapfill layer 1101 comprises is a tungsten (W) seed gapfill layer.

[00123] In one embodiment, the gapfill layer 1101 is deposited using one of deposition techniques, such as but not limited to an ALD, a CVD, PVD, MBE, MOCVD, spin-on or other liner deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

[00124] In some embodiments, deposition of the gapfill layer 1101 includes formation of a seed gapfill layer (not shown). As will be understood by the skilled artisan, a seed gapfill layer is a relatively thin layer of material that can increase the nucleation rate (i.e., growth rate) of the gapfill layer 1101. In some embodiments, the seed gapfill layer is the same material as the gapfill layer 1101 deposited by a different technique. In some embodiments, the seed gapfill layer is a different material than the gapfill layer 1101.

[00125] The formation of the gapfill layer 1101 may be described as using a bulk deposition of the gapfill material to form an overburden (not illustrate) on the top of the substrate followed by planarization to remove the overburden. In some embodiments, the gapfill layer 1101 is formed by a selective deposition process that forms substantially no (e.g., <5% area) overburden on the insulating layer 501.

[00126] Portions of the seed gapfill layer 1101 may then be removed to expose top portions of the insulating layer 501 according to one embodiment, and as illustrated in FIGS. 11A-11C. In one embodiment, the portions of the seed gapfill layer 1101 are removed using one of the chemical-mechanical planarization (CMP) techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

[00127] FIG. 12A is a view 1200 similar to FIG. 11A, after self-aligned selective growth pillars 1201 are formed using the seed gapfill layer 1101 according to one embodiment. FIG. 12B is a top view 1210 of the electronic device depicted in FIG. 12A, and FIG. 12C is a perspective view 1220 of the electronic device depicted in FIG. 12A. As shown in FIGS.12A-12C, an array of the self-aligned selective growth pillars 1201 has the same pattern as the set of the recessed conductive lines 201. As shown in FIGS. 12A-12C, the pillars 1201 extend substantially orthogonally from the top surfaces of the recessed conductive lines 201. As shown in FIGS. 12A-12C, the pillars 1201 extend along the same direction as the recessed conductive lines 201.

[00128] Referring to FIGS. 12A-12C, in one embodiment, the pillars 1201 are selectively grown from the gapfill layer 1101 on portions of the insulating layer 102, on portions of the insulating layer 501, and on the recessed conductive lines 201. In one embodiment, portions of the gapfill layer 1101 above the recessed conductive lines 201 are expanded for example, by oxidation, nitridation, or other process to grow pillars 1201. In one embodiment, the gapfill layer 1101 is oxidized by exposure to an oxidizing agent or oxidizing conditions to transform the metal or metal containing gapfill layer 1101 to metal oxide pillars 1201. In one embodiment, pillars 1201 include an oxide of one or more metals listed above. In more specific embodiment, pillars 1201 include tungsten oxide (e.g., WO, WO3 and other tungsten oxide).

[00129] The oxidizing agent can be any suitable oxidizing agent including, but not limited to, O2, O3, N2O, H2O, H2O2, CO, CO2, N2/Ar, N2/He, N2/Ar/He, ammonium persulphate, organic peroxide agents, such as meta-chloroperbenzoic acid and peracids (e.g. trifluoroperacetic acid, 2,4-dinitroperbenzoic acid, peracetic acid, persulfuric acid, percarbonic acid, perboric acid, and the like), or any combination thereof. In some embodiments, the oxidizing conditions comprise a thermal oxidation, plasma enhanced oxidation, remote plasma oxidation, microwave and radio-frequency oxidation (e.g., inductively coupled plasma (ICP), capacitively coupled plasma (CCP)).

[00130] In one embodiment, the pillars 1201 are formed by oxidation of the seed gapfill layer 1101 at any suitable temperature depending on, for example, the composition of the seed gapfill layer 1101 and the oxidizing agent. In some embodiments, the oxidation occurs at a temperature in an approximate range of about 25 °C to about 800 °C. In some embodiments, the oxidation occurs at a temperature greater than or equal to about 150oC.

[00131] In one embodiment, the height of the pillars 1201 is in an approximate range from about 5 angstroms (Å) to about 10 microns (µm).

[00132] In one or more embodiment, the term“bridging pillars” may be used to refer to pillars 1201 because the pillars, as described below, will be used to form bridging vias filled with conductive lines 1601 that connect recessed conductive lines 201 to conductive lines 1802 without contacting conductive lines 801. In other words, the bridging pillars bridge or span between the lower metallization layer Mx and the upper metallization layer Mz without contacting the middle metallization layer My.

[00133] FIG. 13A is a view 1300 similar to FIG. 12A, and, after an insulating layer 1301 is deposited to overfill and surround the pillars 1201 according to one embodiment. FIG. 13B is a top view 1310 of the electronic device depicted in FIG. 13A, and FIG. 13C is a perspective view 1320 of the electronic device depicted in FIG. 13A. As shown in FIGS. 13A-13C, insulating layer 1301 is deposited on and around the pillars 1201 on the portions of the insulating layer 501 and metallization layer with conductive lines 801.

[00134] In one embodiment, insulating layer 1301 is a low-k gapfill layer. In one embodiment, insulating layer 1301 is a flowable silicon oxide (FSiOx) layer. In at least some embodiments, insulating layer 1301 is an oxide layer, e.g., silicon dioxide (SiO2), or any other electrically insulating layer determined by an electronic device design. In one embodiment, insulating layer 1301 is an interlayer dielectric (ILD). In one embodiment, insulating layer 1301 is a low-k dielectric that includes, but is not limited to, materials such as, e.g., silicon dioxide, silicon oxide, a carbon based material, e.g., a porous carbon film, carbon doped oxide (“CDO”), e.g. carbon doped silicon dioxide, porous silicon dioxide, porous silicon oxide carbide hydride (SiOCH), silicon nitride, or any combination thereof. In one embodiment, insulating layer 1301 is a dielectric material having k-value less than 3. In more specific embodiment, insulating layer 1301 is a dielectric material having k-value in an approximate range from about 2.2 to about 2.7. In one embodiment, insulating layer 1301 includes a dielectric material having k-value less than 2. In one embodiment, insulating layer 1301 represents one of the insulating layers described above with respect to insulating layer 102.

[00135] In one embodiment, insulating layer 1301 is a low-k interlayer dielectric to isolate one metal line from other metal lines. In one embodiment, insulating layer 1301 is deposited using one of deposition techniques, such as but not limited to a CVD, spin-on, an ALD, PVD. MBE, MOCVD, or other low-k insulating layer deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

[00136] FIG. 14A is a view 1400 after a hard mask layer 1402 is deposited on insulating layer 1401 according to one embodiment. FIG.14B is a top view 1410 of the electronic device depicted in FIG. 14A, and FIG. 14C is a perspective view 1420 of the electronic device depicted in FIG. 14A. In one embodiment, hard mask layer 1402 is a metallization layer hard mask. As shown in FIGS. 14A-14C, the hard mask layer 1402 is patterned to define a plurality of trenches 1403. As shown in FIGS. 14A-4C, the trenches 1403 extend along a Y axis (direction) 122 that crosses an X axis (direction) 121 at an angle 123. In one embodiment, Y axis 122 is substantially perpendicular to X axis 121. In one embodiment, patterned hard mask layer 1402 is a carbon hard mask layer, a metal oxide hard mask layer, a metal nitride hard mask layer, a silicon nitride hard mask layer, a silicon oxide hard mask layer, a carbide hard mask layer, or other hard mask layer known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the patterned hard mask layer 1402 is formed using one or more hard mask patterning techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the insulating layer 1401 is etched through a patterned hard mask layer to form trenches 1403 using one or more of etching techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the size of trenches 1403 in the insulating layer 1401 is determined by the size of conductive lines formed later on in a process.

[00137] In one embodiment, hard mask layer 1402 includes a photoresist layer. In one embodiment, hard mask layer 1402 includes one or more hard mask layers. In one embodiment, the insulating layer 1401 is a hard mask layer. In one embodiment, insulating layer 1401 includes a bottom anti-reflective coating (BARC) layer. In one embodiment, insulating layer 1401 includes a titanium nitride (TiN) layer, a tungsten carbide (WC) layer, a tungsten bromide carbide (WBC) layer, a carbon hard mask layer, a metal oxide hard mask layer, a metal nitride hard mask layer, a silicon nitride hard mask layer, a silicon oxide hard mask layer, a carbide hard mask layer, other hard mask layer, or any combination thereof. In one embodiment, insulating layer 1401 represents one of the insulating layers described above. In one embodiment, hard mask layer 1402 is deposited using one or more mask layer deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, insulating layer 1401 is deposited using one of deposition techniques, such as but not limited to a CVD, PVD, MBE, NOCVD, spin-on, or other insulating layer deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the opening 1403 is formed using one or more of the patterning and etching techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

[00138] FIG. 15A is a view 1500 similar to FIG. 14A after at least one self-aligned selectively grown pillars 1201 is selectively removed to form openings 1501 according to one embodiment. FIG. 15B is a top view 1510 of the electronic device depicted in FIG. 15A, and FIG. 15C is a perspective view 1520 of the electronic device depicted in FIG. 15A. As shown in FIGS. 15A-15C, the pillars 1201 are removed selectively to the insulating layer 501, insulating layer 102, insulating layer 1301, and recessed conductive lines 201. As shown in FIGS. 15A-15C, openings 1501 are formed in the insulating layers 1301, 501, and 102. Openings 1501 extend along the same axis as the recessed conductive lines 201. As shown in FIGS. 15A-15C, each opening 1501 has a bottom that is a top surface 203 of recessed conductive lines 201. Generally, the aspect ratio of the opening refers to the ratio of the depth of the opening to the width of the opening. In one embodiment, the aspect ratio of each opening 1501 is in an approximate range from about 1:1 to about 200:1.

[00139] In one embodiment, the pillars 1201 are selectively removed using one or more of the dry and wet etching techniques known to one of ordinary skill in the art of electronic device manufacturing. In one embodiment, the pillars 1201 are selectively wet etched by e.g., 5 wt.% of ammonium hydroxide (NH4OH) aqueous solution at the temperature of about 80 °C. In one embodiment, hydrogen peroxide (H2O2) is added to the 5 wt. % NH4OH aqueous solution to increase the etching rate of the pillars 401. In one embodiment, the pillars 1201 are selectively wet etched using hydrofluoric acid (HF) and nitric acid (HNO3) in a ratio of 1:1. In one embodiment, the pillars 1201 are selectively wet etched using HF and HNO3 in a ratio of 3:7 respectively. In one embodiment, the pillars 1201 are selectively wet etched using HF and HNO3 in a ratio of 4:1, respectively. In one embodiment, the pillars 1201 are selectively wet etched using HF and HNO3 in a ratio of 30%:70%, respectively. In one embodiment, the pillars 1201 including tungsten (W), titanium (Ti), or both titanium and tungsten are selectively wet etched using NH4OH and H2O2 in a ratio of 1:2, respectively. In one embodiment, the pillars 1201 are selectively wet etched using 305 grams of potassium ferricyanide (K3Fe(CN)6), 44.5 grams of sodium hydroxide (NaOH) and 1000ml of water (H2O). In one embodiment, the pillars 1201 are selectively wet etched using diluted or concentrated one or more of the chemistries including hydrochloric acid (HCl), nitric acid (HNO3), sulfuric acid (H2SO4), hydrogen fluoride (HF), and hydrogen peroxide (H2O2). In one or more embodiments, the pillars 1201 are selectively etched using a solution of HF and HNO3, a solution of NH4OH and H2O2, WCl5, WF6, niobium fluoride (NbF5), chlorine with a hydrocarbon. In one or more embodiment, the hydrocarbon can be a monocarbon (e.g. CH4) or multicarbon-based hydrocarbon. In one embodiment, the pillars 1201 are selectively wet etched using HF, HNO3, and acetic acid (CH3COOH) in a ratio of 4:4:3, respectively. In one embodiment, the pillars 1201 are selectively dry etched using a bromotrifluoromethane (CBrF3) reactive ion etching (RIE) technique. In one embodiment, the pillars 1201 are selectively dry etched using chlorine-, fluorine-, bromine-, or any combination thereof, based chemistries. In one embodiment, the pillars 1201 are selectively wet etched using hot or warm Aqua Regia mixture including HCl and HNO3 in a ratio of 3:1, respectively. In one embodiment, the pillars 1201 are selectively etched using alkali with oxidizers (potassium nitrate (KNO3) and lead dioxide (PbO2)).

[00140] FIG. 16A is a view 1600 that is similar to FIG. 15A after a metal film 1601 is deposited in the opening 1501 on recessed conductive lines 201. FIG. 16B is a top view 1610 of the electronic device depicted in FIG. 16A, and FIG. 16C is a perspective view 1620 of the electronic device depicted in FIG. 16A. Metal film 1601 comprises a set of conductive lines which extend along the first direction and aligned with the set of recessed conductive lines 201. [00141] In one embodiment, forming the conductive lines 1601 involves filling the opening 1501 with a layer of conductive material. In one embodiment, a base layer (not shown) is first deposited on the internal sidewalls and bottom of the opening 1501 onto the recessed conductive lines 201, and then the conductive layer is deposited on the base layer. In one embodiment, the base layer includes a conductive seed layer (not shown) deposited on a conductive barrier layer (not shown). The seed layer can include copper (Cu), and the conductive barrier layer can include aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), and the like metals. The conductive barrier layer can be used to prevent diffusion of the conductive material from the seed layer, e.g., copper or cobalt, into the insulating layer 102. Additionally, the conductive barrier layer can be used to provide adhesion for the seed layer (e.g., copper).

[00142] In one embodiment, to form the base layer, the conductive barrier layer is deposited onto the sidewalls and bottom of the opening 1501, and then the seed layer is deposited on the conductive barrier layer. In another embodiment, the conductive base layer includes the seed layer that is directly deposited onto the sidewalls and bottom of the opening 1501. Each of the conductive barrier layer and seed layer may be deposited using any think film deposition technique known to one of ordinary skill in the art of semiconductor manufacturing, e.g., sputtering, blanket deposition, and the like. In one embodiment, each of the conductive barrier layer and the seed layer has the thickness in an approximate range from about 1 nm to about 100 nm. In one embodiment, the barrier layer may be a thin dielectric that has been etched to establish conductivity to the metal layer below. In one embodiment, the barrier layer may be omitted altogether and appropriate doping of the copper line may be used to make a“self-forming barrier”.

[00143] In one embodiment, the conductive layer e.g., copper or cobalt, is deposited onto the seed layer of base layer of copper, by an electroplating process. In one embodiment, the conductive layer is deposited into the opening 1501 using a damascene process known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the conductive layer is deposited onto the seed layer in the opening 1501 using a selective deposition technique, such as but not limited to electroplating, electrolysis, CVD, PVD, MBE, MOCVD, ALD, spin-on, or other deposition techniques know to one of ordinary skill in the art of microelectronic device manufacturing.

[00144] In one embodiment, the choice of a material for conductive layer for the conductive lines 1601 determines the choice of a material for the seed layer. For example, if the material for the conductive lines 1601 includes copper, the material for the seed layer also includes copper. In one embodiment, the conductive lines 1601 include a metal, for example, copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), silver (Ag), platinum (Pt), indium (In), tin (Sn), lead (Pd), antimony (Sb), bismuth (Bi), zinc (Zn), cadmium (Cd), or any combination thereof.

[00145] FIG. 17A is a view 1700 similar to FIG. 16A after hard mask 1402 and insulating layer 1401 are removed. FIG. 17B is a top view 1710 of the electronic device depicted in FIG. 17A, and FIG. 17C is a perspective view 1720 of the electronic device depicted in FIG. 17A. In one embodiment, hard mask layer 1402 is removed using one or more of wet etching, dry etching, or a combination thereof techniques known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, hard mask layer 1402 and insulating layer 1401 are removed using a non-selective etch in a trench first dual damascene process. In one embodiment, hard mask layer 1402 and insulating layer 1401 are etched down to the depth that is determined by time. In another embodiment, hard mask layer 1402 and insulating layer 1401 are etched non-selectively down to an etch stop layer (not shown). In one embodiment, hard mask layer 1402 and insulating layer 1401 are non-selectively etched using one or more of wet etching, dry etching, or a combination thereof techniques known to one of ordinary skill in the art of electronic device manufacturing.

[00146] FIG. 18A is a view 1800 similar to FIG. 17A after a metallization layer is deposited according to one or more embodiment. FIG. 18B is a top view 1810 of the electronic device depicted in FIG. 18A, and FIG. 18C is a perspective view 1820 of the electronic device depicted in FIG. 18A. In one or more embodiment, a metallization layer is formed comprised conductive lines 1801 and conductive lines 1802. The conductive lines 1802 extend along the first direction and are aligned with the set of conductive lines 201.

[00147] An upper metallization layer Mz includes a set of conductive lines 1802 that extend on portions of insulating layer 1301. As shown in FIG. 18A-18C, conductive lines 1802 extend along Y axis 122. The fully self-aligned bridging via filled with conductive lines 1601 is between the lower metallization layer comprising recessed conductive lines 201 that extend along X axis 121 and the upper metallization layer comprising conductive lines 1802. As

shown in FIGS. 18A-18C, the bridging via filled with conductive lines 1601 is self-aligned along the Y axis 122 to conductive lines 1802.

[00148] In one embodiment, forming the conductive lines 1802 and 1801 and filled via with conductive lines 1601 involves depositing a layer of conductive material on the top surface of insulating layer 1301. In one embodiment, a base layer (not shown) is first deposited on the top surface of the insulating layer 1301, and then the conductive layer is deposited on the base layer. In one embodiment, the base layer includes a conductive seed layer (not shown) deposited on a conductive barrier layer (not shown). The seed layer can include copper, and the conductive barrier layer can include aluminum, titanium, tantalum, tantalum nitride, and the like metals. The conductive barrier layer can be used to prevent diffusion of the conductive material from the seed layer, e.g., copper, into the insulating layer. Additionally, the conductive barrier layer can be used to provide adhesion for the seed layer (e.g., copper).

[00149] In one embodiment, to form the base layer, the conductive barrier layer is deposited on the insulating layer 1301, and then the seed layer is deposited on the conductive barrier layer. In another embodiment, the conductive base layer includes the seed layer that is directly deposited on the insulating layer 1301. Each of the conductive barrier layer and seed layer may be deposited using any thin film deposition technique known to one of ordinary skill in the art of semiconductor manufacturing, e.g., sputtering, blanket deposition, and the like. In one embodiment, each of the conductive barrier layer and the seed layer has the thickness in an approximate range from about 1 nm to about 100 nm. In one embodiment, the barrier layer may be a thin dielectric that has been etched to establish conductivity to the metal layer below. In one embodiment, the barrier layer may be omitted altogether and appropriate doping of the copper line may be used to make a“self-forming barrier”.

[00150] In one embodiment, the conductive layer e.g., copper or cobalt, is deposited onto the seed layer of base later of copper, by an electroplating process. In one embodiment, the conductive layer is deposited using a damascene process known to one of ordinary skill in the art of microelectronic device manufacturing. In one embodiment, the conductive layer is deposited onto the seed layer using a selective deposition technique, such as but not limited to electroplating, electrolysis, a CVD, PVD, MBE, MOCVD, ALD, spin-on, or other deposition techniques known to one of ordinary skill in the art of microelectronic device manufacturing.

[00151] In one embodiment, the choice of a material for conductive layer for the conductive lines 1802 and 1801 determines the choice of a material for the seed layer. For example, if the material for the conductive lines 1802 and 1801 includes copper, the material for the seed layer also includes copper. In one embodiment, the conductive lines 1802 and 1801 include a metal, for example, copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), silver (Ag), platinum (Pt), indium (In), tin (Sn), lead (Pb), antimony (Sb), bismuth (Bi), zinc (Zn), cadmium (Cd), or any combination thereof.

[00152] In alternative embodiments, examples of the conductive materials that may be used for the conductive lines 1802 and 1801 include metals, e.g., copper, tantalum, tungsten, ruthenium, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof.

[00153] In one non-limiting example, the thickness of the conductive lines 1802 and 1802 is in an approximate range from about 15 nm to about 1000 nm. In one non-limiting example, the thickness of the conductive lines 1802 is from about 20 nm to about 200 nm. In one non-limiting example, the width of the conductive lines 1802 is in an approximate range from about 5 nm to about 500 nm. In one non-limiting example, the spacing (pitch) between the conductive lines 1802 is from about 2 nm to about 500 nm. In more specific non-limiting example, the spacing (pitch) between the conductive lines 1802 is from about 5 nm to about 50 nm.

[00154] In one or more embodiment, the term“bridging vias” may be used to refer to via opening 1501 because the when filled with conductive lines 1601, the filled vias connect the recessed conductive lines 201 to the conductive lines 1802 without contacting the conductive lines 801.

[00155] In the foregoing specification, embodiments of the disclosure have been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.