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1. WO2020159800 - RÉSEAU DE NEURONES ARTIFICIELS À MÉMOIRE INTÉGRÉE

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CLAIMS

What is claimed is:

1. An integrated-circuit neural network (neural network IC) comprising:

a storage array; and

a plurality of multiply-accumulate (MAC) units coupled in a chain, each multiply- accumulate unit having:

a digital input port to receive a matrix of digital-weight values from the storage array; an analog input port to receive a matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value; and

multiply-adder circuitry to generate a matrix of analog output signals by convolving the matrix of digital- weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital-weight values.

2. The neural network IC of claim 1 wherein the multiply-adder circuitry comprises circuitry to:

multiply a column of N analog input signals within the matrix of analog input signals with a row of N digital weight values within the matrix of digital weight values to produce, as multiplication products, N output currents on respective current- contribution conductors; and

an output conductor coupled to each of the current-contribution conductors to yield, as a respective analog output signal within the matrix of analog output signals, a wired sum of the N output currents.

3. The neural network IC of claim 2 wherein the circuitry to multiply the column of N analog input signals with the row of N digital weight values comprises N multiplier circuits for which the current-contribution conductors constitute respective signal outputs.

4. The neural network IC of claim 3 wherein each multiplier circuit of the N multiplier

circuits receives a respective one of the N analog input signals and a respective one of the N digital weight values and comprises circuitry to switchably couple one or more of a plurality of current sources to the respective current-contribution conductor in accordance with the one of the N digital weight values.

5. The neural network IC of claim 4 wherein the circuitry to switchably couple one or more of the plurality of current sources to the respective current-contribution conductor comprises circuitry to switchably couple a first one of the current sources to the current- contribution conductor according to a state of a most significant bit of the one of the digital weighting values and to switchably couple a second one of the current sources to the current-contribution conductor according to a state of a less significant bit of the one of the digital weighting values.

6. The neural network IC of claim 5 wherein current flow from the first one of the current sources is twice the current flow from the second one of the current sources.

7. The neural network IC of claim 4 wherein current flow from each of the plurality of

current sources varies between maximum and minimum current levels in accordance with the respective one of the N analog input signals.

8. The neural network IC of claim 4 wherein at least one of the MAC units additionally

comprises a current-mode latch to store values representative of the matrix of analog output signals generated by an upstream MAC unit at conclusion of a first interval and to output, based on the values stored within the current-mode latch, a matrix of analog input signals to the multiply-adder circuitry within the at least one of the MAC units during a second interval subsequent to the first interval.

9. The neural network IC of claim 8 wherein the current-mode latch comprises:

a capacitive element that is charged to a voltage potential corresponding to a current-mode signal within the matrix of analog output signals to store a value representative of the first current-mode signal at conclusion of the first interval; and

a voltage-controlled current source to which the voltage potential of the capacitive element is applied to generate a current-mode signal within the matrix of analog input signals supplied to the multiply-adder within the at least one of the MAC units during the second interval.

10. The neural network IC of claim 1 wherein the storage array comprises a dynamic random access memory (DRAM) having a plurality of column output lines that extend across rows of DRAM cells, and wherein the MAC units are coupled to the column output lines to receive the digital-weight values.

11. The neural network IC of claim 10 wherein the DRAM comprises a plurality of sense

amplifier banks and control circuitry to concurrently activate two or more rows of the DRAM cells such that contents of two or more rows of DRAM cells are transferred to and simultaneously resident within respective subsets of the sense amplifier banks.

12. The neural network IC of claim 11 wherein the control circuitry to concurrently activate the two or more rows of the DRAM cells comprises circuitry to commence activation of a

first row of the DRAM cells prior to executing a precharge operation with respect to a previously activated second row of the DRAM cells, and wherein first weighting data transferred from the second row of the DRAM cells to a first subset of the sense amplifier banks is provided from the first subset of the sense amplifier banks to one or more of the MAC units during transfer of second weighting data from the first row of the DRAM cells to a second subset of the sense amplifier banks.

13. A method of operation within an integrated-circuit neural network (neural network IC) having a plurality of multiply-accumulate (MAC) units coupled in a chain, the method comprising:

receiving, via a digital input port of each MAC unit, a respective matrix of digital- weight values from a storage array implemented within the neural network IC;

receiving, via an analog input port of each MAC unit, a respective matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value; and

generating, within each MAC unit, a matrix of analog output signals by convolving the matrix of digital-weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital-weight values.

14. The method of claim 13 wherein the convolving the matrix of digital-weight values with the matrix of analog input signals comprises multiplying a column of N analog input signals within the matrix of analog input signals with a row of N digital weight values within the matrix of digital weight values to produce, as multiplication products, N output currents on respective current-contribution conductors, current-contribution conductors being coupled to a common output conductor to yield, as a respective analog output signal within the matrix of analog output signals, a wired sum of the N output currents.

15. The method of claim 14 wherein multiplying the column of N analog input signals with the row of N digital weight values multiplying respective ones of the N analog input signals with corresponding ones of the N digital weight values within N multiplier circuits for which the current-contribution conductors constitute respective signal outputs.

16. The method of claim 15 wherein multiplying respective ones of the N analog input signals with corresponding ones of the N digital weight values comprises, for each one of the analog input signals and each corresponding one of the N digital weight values, switchably coupling one or more of a plurality of current sources to the respective current-contribution conductor in accordance with the one of the N digital weight values.

17. The method of claim 16 wherein switchably coupling one or more of the plurality of current sources to the respective current-contribution conductor comprises switchably coupling a first one of the current sources to the current-contribution conductor according to a state of a most significant bit of the one of the digital weighting values and switchably coupling a second one of the current sources to the current-contribution conductor according to a state of a less significant bit of the one of the digital weighting values.

18. The method of claim 17 wherein current flow from the first one of the current sources is twice the current flow from the second one of the current sources.

19. The method of claim 16 wherein current flow from each of the plurality of current sources varies between maximum and minimum current levels in accordance with the respective one of the N analog input signals.

20. The method of claim 13 wherein the storage array comprises a dynamic random access memory (DRAM) having a plurality of column output lines that extend across rows of DRAM cells, and wherein receiving, via a digital input port of each MAC unit, a respective matrix of digital-weight values from a storage array implemented within the neural network IC comprises receiving the respective matrix of digital- weight values via the column output lines.

21. The method of claim 20 further comprising concurrently activating two or more rows of the DRAM cells such that contents of two or more rows of DRAM cells are transferred to and simultaneously resident within respective subsets of sense amplifier banks within the DRAM.

22. An integrated-circuit neural network (neural network IC) comprising:

a storage array;

a plurality of multiply-accumulate (MAC) units coupled in a chain, each multiply- accumulate unit including:

means for receiving a respective matrix of digital- weight values from the storage array;

means for receiving a respective matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value; and

means for generating a matrix of analog output signals by convolving the matrix of digital-weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital- weight values.