WHAT IS CLAIMED IS:

1. A binary arithmetic decoding apparatus comprising:

a first pair of look-up tables;

a first multiplexer to select between an output of a first look-up table of said first pair of look-up tables and an output of a second look-up table of said first pair of look-up tables;

a second pair of look-up tables;

a third pair of look-up tables;

a second multiplexer to select between an output of a first look-up table of said second pair of look-up tables and an output of a first look-up table of said third pair of look-up tables; and

a third multiplexer to select between an output of a second look-up table of said second pair of look-up tables and an output of a second look-up table of said third pair of look-up tables;

wherein said first, second and third multiplexers are all controlled by a control signal that is common to said first, second and third multiplexers.

2. The apparatus of claim 1, wherein said pairs of look-up tables and said multiplexers are part of a circuit for decoding a compression-encoded video signal.

3. The apparatus of claim 2, wherein said pairs of look-up tables and said multiplexers are included in binary arithmetic decoding engines.

4. The apparatus of claim 2, wherein:

if a most likely bin value is selected to be a current output bin value, then:

the first multiplexer is controlled to select the output of the first look-up table of said first pair of look-up tables;

the second multiplexer is controlled to select the output of the first look-up table of said second pair of look-up tables; and

the third multiplexer is controlled to select the output of the second look-up table of said second pair of look-up tables; and

if a least likely bin value is selected to be a current output bin value, then:

the first multiplexer is controlled to select the output of the second look-up table of said first pair of look-up tables;

the second multiplexer is controlled to select the output of the first look-up table of said third pair of look-up tables; and

the third multiplexer is controlled to select the output of the second look-up table of said third pair of look-up tables.

5. The apparatus of claim 4, wherein:

the most likely bin value is a first most likely bin value that is provided as an input to a first binary arithmetic decoder stage;

the least likely bin value is a first least likely bin value that is an inverse of the first most likely bin value; and

the current output bin value is a first current output bin value output from the first binary arithmetic decoder stage;

the apparatus further comprising:

a fourth multiplexer to select between an output of said second multiplexer and an output of said third multiplexer;

wherein:

said fourth multiplexer is controlled to select the output of the second multiplexer if a second binary arithmetic decoder stage outputs, as a second current output bin value, a second most likely bin value that is provided as an input to the second binary arithmetic decoder stage; and

said fourth multiplexer is controlled to select the output of the third multiplexer if the second binary arithmetic decoder stage outputs, as said second current output bin value, a second least likely bin value that is an inverse of the second most likely bin value.

6. The apparatus of claim 5, further comprising:

a fourth pair of look-up tables;

a fifth pair of look-up tables;

a fifth multiplexer to select between an output of a first look-up table of said fourth pair of look-up tables and an output of a first look-up table of said fifth pair of look-up tables;

a sixth multiplexer to select between an output of a second look-up table of said fourth pair of look-up tables and an output of a second look-up table of said fifth pair of look-up tables;

a sixth pair of look-up tables;

a seventh pair of look-up tables;

a seventh multiplexer to select between an output of a first look-up table of said sixth pair of look-up tables and an output of a first look-up table of said seventh pair of look-up tables;

an eighth multiplexer to select between an output of a second look-up table of said sixth pair of look-up tables and an output of a second look-up table of said seventh pair of look-up tables;

a ninth multiplexer to select between an output of the fifth multiplexer and an output of the sixth multiplexer; and

a tenth multiplexer to select between an output of the seventh multiplexer and an output of the eighth multiplexer.

7. The apparatus of claim 6, wherein:

if the first most likely bin value is selected by the first binary arithmetic decoder stage to be the first current output bin value, then: the fifth multiplexer is controlled to select the output of the first look-up table of said fourth pair of look-up tables;

the sixth multiplexer is controlled to select the output of the second look-up table of said fourth pair of look-up tables;

the seventh multiplexer is controlled to select the output of the first look-up table of said sixth pair of look-up tables; and

the eighth multiplexer is controlled to select the output of the second lookup table of said sixth pair of look-up tables; and

if the first least likely bin value is selected by the first binary arithmetic decoder stage to be the first current output bin value, then:

the fifth multiplexer is controlled to select the output of the first look-up table of said fifth pair of look-up tables;

the sixth multiplexer is controlled to select the output of the second look-up table of said fifth pair of look-up tables;

the seventh multiplexer if controlled to select the output of the first look-up table of said seventh pair of look-up tables; and

the eighth multiplexer is controlled to select the output of the second lookup table of said seventh pair of look-up tables.

8. The apparatus of claim 7, wherein:

if the second binary arithmetic decoder stage outputs the second most likely bin value as the second current output bin value, then:

the ninth multiplexer is controlled to select the output of the fifth multiplexer; and

the tenth multiplexer is controlled to select the output of the seventh multiplexer; and

if the second binary arithmetic decoder stage outputs the second least likely bin value as the second current output bin value, then: the ninth multiplexer is controlled to select the output of the sixth multiplexer; and

the tenth multiplexer is controlled to select the output of the eighth multiplexer.

9. The apparatus of claim 2, wherein the circuit includes at least one context modeler and a plurality of binary arithmetic decoder stages, of which at least one is coupled to at least one of the at least one context modeler, said look-up tables to provide data to said binary arithmetic decoder stages.

10. The apparatus of claim 9, wherein each binary arithmetic decoder stage of said plurality of binary arithmetic decoder stages is coupled either to one of said at least one context modelers or to a preceding one of said plurality of binary arithmetic decoder stages.

11. A system comprising:

a video signal source to supply a compression-encoded video signal; and

a video decoder coupled to the video signal source to decode the compression-encoded video signal supplied by the video signal source, the video decoder comprising:

a first pair of look-up tables;

a first multiplexer to select between an output of a first look-up table of said first pair of look-up tables and an output of a second look-up table of said first pair of look-up tables;

a second pair of look-up tables;

a third pair of look-up tables;

a second multiplexer to select between an output of a first look-up table of said second pair of look-up tables and an output of a first look-up table of said third pair of look-up tables; and a third multiplexer to select between an output of a second look-up table of said second pair of look-up tables and an output of a second look-up table of said third pair of look-up tables;

wherein said first, second and third multiplexers are all controlled by a control signal that is common to said first, second and third multiplexers.

12. The system of claim 11, wherein:

if a most likely bin value is selected to be a current output bin value, then:

the first multiplexer is controlled to select the output of the first look-up table of said first pair of look-up tables;

the second multiplexer is controlled to select the output of the first look-up table of said second pair of look-up tables; and

the third multiplexer is controlled to select the output of the second look-up table of said second pair of look-up tables; and

if a least likely bin value is selected to be a current output bin value, then:

the first multiplexer is controlled to select the output of the second look-up table of said first pair of look-up tables;

the second multiplexer is controlled to select the output of the first look-up table of said third pair of look-up tables; and

the third multiplexer is controlled to select the output of the second look-up table of said third pair of look-up tables.

13. The system of claim 12, wherein:

the most likely bin value is a first most likely bin value that is provided as an input to a first binary arithmetic decoder stage;

the least likely bin value is a first least likely bin value that is an inverse of the first most likely bin value; and

the current output bin value is a first current output bin value output from the first binary arithmetic decoder stage;

the system further comprising:

a fourth multiplexer to select between an output of said second multiplexer and an output of said third multiplexer;

wherein:

said fourth multiplexer is controlled to select the output of the second multiplexer if a second binary arithmetic decoder stage outputs, as a second current output bin value, a second most likely bin value that is provided as an input to the second binary arithmetic decoder stage; and

said fourth multiplexer is controlled to select the output of the third multiplexer if the second binary arithmetic decoder stage outputs, as said second current output bin value, a second least likely bin value that is an inverse of the second most likely bin value.

14. The system of claim 13, further comprising:

a fourth pair of look-up tables;

a fifth pair of look-up tables;

a fifth multiplexer to select between an output of a first look-up table of said fourth pair of look-up tables and an output of a first look-up table of said fifth pair of look-up tables;

a sixth multiplexer to select between an output of a second look-up table of said fourth pair of look-up tables and an output of a second look-up table of said fifth pair of look-up tables;

a sixth pair of look-up tables;

a seventh pair of look-up tables;

a seventh multiplexer to select between an output of a first look-up table of said sixth pair of look-up tables and an output of a first look-up table of said seventh pair of look-up tables;

an eighth multiplexer to select between an output of a second look-up table of said sixth pair of look-up tables and an output of a second look-up table of said seventh pair of look-up tables;

a ninth multiplexer to select between an output of the fifth multiplexer and an output of the sixth multiplexer; and

a tenth multiplexer to select between an output of the seventh multiplexer and an output of the eighth multiplexer.

15. The system of claim 14, wherein:

if the first most likely bin value is selected by the first binary arithmetic decoder stage to be the first current output bin value, then:

the fifth multiplexer is controlled to select the output of the first look-up table of said fourth pair of look-up tables;

the sixth multiplexer is controlled to select the output of the second look-up table of said fourth pair of look-up tables;

the seventh multiplexer is controlled to select the output of the first look-up table of said sixth pair of look-up tables; and

the eighth multiplexer is controlled to select the output of the second lookup table of said sixth pair of look-up tables; and

if the first least likely bin value is selected by the first binary arithmetic decoder stage to be the first current output bin value, then:

the fifth multiplexer is controlled to select the output of the first look-up table of said fifth pair of look-up tables;

the sixth multiplexer is controlled to select the output of the second look-up table of said fifth pair of look-up tables;

the seventh multiplexer if controlled to select the output of the first look-up table of said seventh pair of look-up tables; and

the eighth multiplexer is controlled to select the output of the second lookup table of said seventh pair of look-up tables.

16. The system of claim 15, wherein:

if the second binary arithmetic decoder stage outputs the second most likely bin value as the second current output bin value, then:

the ninth multiplexer is controlled to select the output of the fifth multiplexer; and

the tenth multiplexer is controlled to select the output of the seventh multiplexer; and

if the second binary arithmetic decoder stage outputs the second least likely bin value as the second current output bin value, then:

the ninth multiplexer is controlled to select the output of the sixth multiplexer; and

the tenth multiplexer is controlled to select the output of the eighth multiplexer.

17. An apparatus comprising:

a first binary arithmetic decoder stage;

a first group of look-up tables coupled to the first binary arithmetic decoder stage to provide update and range data to the first binary arithmetic decoder stage;

a second binary arithmetic decoder stage coupled to the first binary arithmetic decoder stage to receive offset and range data from the first binary arithmetic decoder stage;

a second group of look-up tables;

a third group of look-up tables;

a first group of three multiplexers, each multiplexer of said first group of multiplexers to receive one input from a respective look-up table of the second group of look-up tables and to receive a second input from a respective look-up table of the third group of look-up tables and having an output coupled to said second binary arithmetic decoder stage;

a third binary arithmetic decoder stage coupled to the second binary arithmetic decoder stage to receive offset and range data from the second binary arithmetic decoder stage;

a fourth group of look-up tables;

a fifth group of look-up tables;

a sixth group of look-up tables;

a seventh group of look-up tables;

a second group of three multiplexers, each multiplexer of said second group of multiplexers to receive one input from a respective look-up table of said fourth group of look-up tables and to receive a second input from a respective look-up table of the fifth group of look-up tables;

a third group of three multiplexers, each multiplexer of said third group of multiplexers to receive one input from a respective look-up table of said sixth group of look-up tables and to receive a second input from a respective look-up table of said seventh group of look-up tables; and

a fourth group of three multiplexers, each multiplexer of said fourth group of multiplexers to receive one input from a respective multiplexer of said second group of multiplexers and to receive a second input from a respective multiplexer of said third group of multiplexers and having an output coupled to said third binary arithmetic stage.

18. The apparatus of claim 17, wherein each of said binary arithmetic decoder stages includes a respective stage multiplexer to select between two output bin values.

19. The apparatus of claim 18, wherein each of said binary arithmetic decoder stages includes a respective compare block to compare a range value and an offset value and coupled to the respective stage multiplexer to control the respective stage multiplexer.

20. The apparatus of claim 19, wherein each of said binary arithmetic decoder stages further includes at least three further respective stage multiplexers controlled by the respective compare block.