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1. WO2020160159 - TEST STRUCTUREL DANS UN SYSTÈME D'UN SYSTÈME SUR PUCE (SOC) À L'AIDE D'UN PORT D'INTERFACE PÉRIPHÉRIQUE

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[ EN ]

CLAIMS

What is claimed is:

1. A method of in-system structural testing of a system-on-chip (SoC) using a peripheral interface port, the method comprising:

enabling a scan interface controller of the SoC through the peripheral interface port; and

streaming structural test patterns in the SoC through the scan interface controller.

2. The method of claim 1, in which the peripheral interface port comprises a universal serial bus (USB) port and the scan interface controller comprises a low pin count (LPC) controller.

3. The method of claim 2, in which enabling the scan interface controller comprises:

disconnecting a USB device controller;

re-initializing the USB device controller as an LPC scan device; and

configuring the LPC controller as an LPC scan controller according to a USB-LPC test mode.

4. The method of claim 2, further comprising transmitting a command packet to a USB device controller to enter a USB-LPC test mode.

5. The method of claim 1, in which streaming comprises:

reading automated test equipment (ATE) vectors; and

transmitting ATE vectors through the peripheral interface port.

6. The method of claim 1, in which streaming further comprises:

writing a burst of automatic test equipment (ATE) vectors to the peripheral interface port;

reading a burst of result ATE vector data through the peripheral interface port; and

comparing the result ATE vector data to expected ATE vector data.

7. The method of claim 1, in which enabling further comprises configuring a device under test (DUT) of the SoC into a USB-LPC test mode.

8. An apparatus configured for in-system structural testing of a system-on-chip (SoC) through a peripheral interface port, comprising:

a scan interface controller communicably coupled to the peripheral interface port, in which the scan interface controller is enabled through the peripheral interface port and configured to stream structural test patterns in the SoC, in which the structural test patterns are received through the peripheral interface port.

9. The apparatus of claim 8, further comprising a test interface coupled to the SoC, in which the scan interface is further configured to automated test equipment (ATE)/structural testing patterns from the test interface to a device under test (DUT), and configured to reading test result data from the DUT.

10. The apparatus of claim 9, in which the test interface comprises a 64-bit test interface of data, clocked according to a super-speed (SS) mode or a super-speed plus (SSP) mode to drive the ATE/structural test patterns during a system level test (SLT).

11. The apparatus of claim 8, in which the peripheral interface port comprises a universal serial bus (USB) port.

12. The apparatus of claim 8, in which the scan interface controller comprises a low pin count (LPC) controller.

13. The apparatus of claim 8, comprising one of one of a computing system, mobile computing device, Internet of Things device, or virtual reality or augmented reality system, incorporating the scan interface controller.

14. A non-transitory computer-readable medium having program code recorded thereon for transitioning gear speeds for in-system structural testing of a system-on-chip (SoC) using a peripheral interface port, the program code executed by a processor and comprising:

program code to enable a scan interface controller of the SoC through the peripheral interface port; and

program code to stream structural test patterns in the SoC through the scan interface controller.

15. The non-transitory computer-readable medium of claim 14, in which the peripheral interface port comprises a universal serial bus (USB) port and the scan interface controller comprises a low pin count (LPC) controller.

16. The non-transitory computer-readable medium of claim 15, in which the program code to enable the scan interface controller comprises:

program code to disconnect a USB device controller;

program code to re-initialize the USB device controller as an LPC scan device; and

program code to configure the LPC controller as an LPC scan controller according to a USB-LPC test mode.

17. The non-transitory computer-readable medium of claim 15, further comprising program code to transmit a command packet to a USB device controller to enter a USB-LPC test mode.

18. The non-transitory computer-readable medium of claim 14, in which the program code to stream further comprises:

program code to read automated test equipment (ATE) vectors; and

program code to transmit ATE vectors through the peripheral interface port.

19. The non-transitory computer-readable medium of claim 18, in which the program code to stream further comprises:

program code to writing a burst of automatic test equipment (ATE) vectors to the peripheral interface port;

program code to read a burst of result ATE vector data through the peripheral interface port; and

program code to compare the result ATE vector data to expected ATE vector data.

20. The non-transitory computer-readable medium of claim 14, in which the program code to enable further comprises program code to configure a device under test (DUT) of the SoC into a USB-LPC test mode.