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1. WO1995006280 - APPAREIL ET PROCEDE PERMETTANT D'ACCELERER LE TRANSFERT DE DONNEES

Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

[ EN ]

What is claimed is:
1. A method for accelerating the transfer of data from a data source to a memory coupled to a central processing unit (CPU), comprising the steps of:
monitoring signals from said CPU to determine whether data transfer from said data source to said memory is desired;
generating an optimized instruction set for execution by said CPU for effecting data transfer from said data source to said memory; and
sending said optimized instruction set to said CPU in response to a determination that data transfer is desired.

2. The method of claim 1 , further comprising the step of:
executing said optimized instruction set to optimally transfer data from said data source to said memory.

3. The method of claim 1, wherein said optimized instruction set is generated in real time.

4. The method of claim 1, wherein the step of generating comprises the steps of:
providing an instruction for causing said CPU to move data from said data source to a destination address in said memory;
receiving data and said destination address from said data source; and
merging said data and said address with said instruction to produce said optimized . instruction set.

5. The method of claim 1, wherein the step of sending comprises the steps of: receiving address signals from said CPU;
decoding said address signals to determine whether the address is within a selected range; and
sending said optimized instruction set only if said address is within said selected range.

6. The method of claim 1 , wherein the step of generating comprises the steps of:
providing a register having a first storage section having stored therein an instruction for causing said CPU to transfer data to a destination address in said memory; receiving data and said destination address from said data source; and
storing said data and said address in additional storage sections in said register.

7. The method of claim 6, wherein the step of sending comprises the steps of: accessing each of said storage sections in said register; and
outputting the contents of each of said storage sections to said CPU.

8. The method of claim 1, wherein the step of monitoring comprises the steps of:
receiving control and address signals from said CPU; and
processing said signals to determine whether data transfer from said data source to said memory is desired.

9. The method of claim 8, wherein the step of processing includes the step of: decoding said address signals to determine whether the address is within a selected range.

10. An apparatus for accelerating the transfer of data from a data source to a memory coupled to a central processing unit (CPU), comprising:
a determiner for receiving and processing signals from said CPU to determine whether data transfer from said data source to said memory is desired, said determiner generating a run control signal in response to a determination that data transfer is desired; an instruction generator, having an output, for generating an optimized instruction set for execution by said CPU for effecting data transfer from said data source to said memory; and
a coupling circuit coupled to the output of said instruction generator responsive to said run control signal to send said optimized instruction set to said CPU to enable said CPU to execute said instructions to transfer data from said data source to said memory.

11. The apparatus of claim 10, wherein said instruction generator generates said optimized instruction set in real time.

12. The apparatus of claim 10, wherein said determiner comprises:
a decoder for receiving address signals from said CPU and decoding said address signals to determine whether the address is within a selected range, said decoder generating said run control signal in response to a determination that said address is within said selected range.

13. The apparatus of claim 10, wherein said instruction generator has inputs for receiving data and a destination address from said data source, and wherein said generator incorporates said data and destination address into said optimized instruction set.

14. The apparatus of claim 10, wherein said instruction generator comprises: a register having a first storage section for storing an instruction for causing said

CPU to transfer data to a destination address in said memory, and a plurality of additional storage sections, said register receiving data and said destination address from said data source and storing said data and destination* address into said additional storage sections.

15. The apparatus of claim 14, wherein said register receives address signals from said CPU and responds by selectively outputting the contents of each of said storage sections to said coupling circuit.

16. The apparatus of claim 10, wherein said determiner generates an idle control signal in response to a determination that data transfer is not desired, and wherein said coupling circuit responds to said idle control signal by terminating the sending of said optimized instruction set to said CPU.

17. The apparatus of claim 16, wherein said coupling circuit comprises:
a state switch having an idle port coupled to an instruction memory, and an output port coupled to said CPU, said state switch coupling said idle port to said output port in response to said idle control signal.

18. The apparatus of claim 10, wherein said coupling circuit comprises:
a state switch having a run port coupled to the output of said instruction generator, and an output port coupled to said CPU, said state switch coupling said run port to said output port in response to said run control signal to send said optimized instruction set to said CPU for execution thereby.

19. The apparatus of claim 18, wherein said state switch has a done port, and wherein said apparatus further comprises an RTS register coupled to said done port for storing an instruction for causing said CPU to terminate the transfer of data into said memory, said state switch coupling said done port to said output port when the transfer of data from said data source to said memory is complete.