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1. WO1995007543 - FABRICATION ET STRUCTURE DE DISPOSITIFS EMETTEURS D'ELECTRONS POSSEDANT UNE DENSITE D'INTEGRATION ELEVEE

Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

[ EN ]

WHAT IS CLAIMED IS:
1. A method comprising the steps of:
creating a structure in which an electrically insulating layer lies over a patterned lower
electrically non-insulating region comprising a group of generally parallel lines situated over electrically insulating material of a substrate, a multiplicity of pores extending through the insulating layer down to the lower non-insulating region; and
introducing electrically non-insulating filament material into the pores to form corresponding electron-emissive filaments therein, the lower end of each filament contacting the lower non-insulating region.

2. A method as in Claim 1 further including the step of sharpening the upper ends of the filaments to form sharpened tips.

3. A method comprising the steps of:
creating a structure in which an electrically insulating layer lies over an electrically resistive portion of a lower electrically non-insulating region that also includes an electrically conductive portion situated under the resistive portion, a multiplicity of pores extending through the insulating layer down to the resistive portion; and
introducing electrically non-insulating filament material into the pores to form corresponding electron-emissive filaments therein, the lower end of each filament contacting the resistive portion.

4. A method as in Claim 3 wherein the lower non-insulating region is a patterned layer comprising a group of generally parallel lines, each being formed with segments of both portions of the lower non-insulating region.

5. A method as in any of Claims 1 - 4 further including the step of removing a thickness of the insulating layer sufficient to enable each filament to extend outward beyond the remainder of the structure.

6. A method comprising the steps of:
creating a structure in which an electrically insulating layer lies over a lower electrically non-insulating region, a multiplicity of pores extending through the insulating layer down to the lower non-insulating region;
introducing electrically non-insulating filament material into the pores to form corresponding electron-emissive filaments therein, the lower end of each filament contacting the lower non-insulating region; and
providing a patterned electrically non-insulating gate layer over specified material of the insulating layer, gate openings respectively extending through the gate layer at locations generally centered on the filaments such that the filaments are separated from the gate layer.

7. A method as in Claim 6 wherein the providing step comprises:
producing electrically conductive caps over the upper ends of the filaments, each cap being situated over one of the filaments and having a lateral
periphery that encloses the lateral periphery of the underlying filament along the bottom of that cap;
removing part of the thickness of the insulating layer;
depositing electrically non-insulating gate material over the remainder of the insulating layer in the space generally below the space between the caps; and substantially removing the caps including any of the gate material on the caps, whereby the gate layer comprises the remaining gate material.

8. A method as in Claim 6 wherein the providing step comprises:
producing electrically conductive caps over the upper ends of the filaments, each cap being situated over one of the filaments and having a lateral
periphery that encloses the lateral periphery of the underlying filament along the bottom of that cap;
forming the gate layer in the space between the caps; and
substantially removing the caps.

9. A method as in Claim 8 wherein the forming step comprises:
depositing a blanket layer of electrically non-insulating gate material over the insulating layer and the caps; and
selectively removing the gate material over the caps so as to expose them, whereby the gate layer comprises the remaining gate material.

10. A method comprising the steps of:
creating a structure in which an electrically non-insulating gate layer lies over an electrically insulating layer situated over a lower electrically non-insulating region, gate openings extending through the gate layer to expose corresponding surface portions of the insulating layer;
forming a multiplicity of pores through the insulating layer down to the lower non-insulating region, each pore being formed through part of the exposed surface portion at a corresponding one of the gate openings such that each pore is generally centered on the corresponding gate opening and is narrower than the corresponding gate opening along the bottom of the gate layer; and
introducing electrically non-insulating filament material into the pores to form corresponding electron-emissive filaments separated from the gate layer, the lower end of each filament contacting the lower non-insulating region.

11. A method as in Claim 10 wherein the creating step entails:
providing the structure with (a) a second
electrically insulating layer situated over the gate layer and (b) a second electrically non-insulating layer situated over the second insulating layer;
forming openings through the second non-insulating layer down to the second insulating layer;
forming corresponding apertures through the second insulating layer down to the gate layer such that each aperture in the second insulating layer is generally centered on the corresponding opening in the second non-insulating layer; and
etching the gate layer through the apertures in the insulating layer to form the gate openings such that each gate opening is generally centered on the corresponding aperture in the second dielectric layer.

12. A method as in any of Claims 6 - 11 further including the step of removing material of the
insulating layer exposed through the gate openings to form cavities situated around the filaments so that the filaments extend outward beyond the remainder of the insulating layer, the cavities extending at least partway down to the lower non-insulating region.

13. A method as in any of Claims 1 - 12 wherein the creating step comprises:
forming charged-particle tracks through a track layer constituted with electrically insulating material provided over the lower non-insulating region; and
etching the track layer along the charged-particle tracks to form pores through the track layer and thereby convert it into the insulating layer.

14. A method as in any of Claims 1 - 13 wherein the introducing step comprises electrochemically depositing the filament material into the pores starting from the lower non-insulating region.

15. A method comprising the steps of:
creating an electrically insulating track layer over a lower electrically non-insulating region;
subsequently forming charged-particle tracks through the track layer;
etching the track layer along the charged-particle tracks to form a multiplicity of pores extending through the track layer down to the lower non-insulating region; and
electrochemically introducing electrically non-insulating filament material into the pores starting from the lower non-insulating region to create
corresponding electron-emissive filaments whose lower ends contact the lower non-insulating region.

16. A method as in Claim 15 further including the step of removing a thickness of the track layer
sufficient to enable each filament to extend outward beyond the remainder of the structure.

17. A method comprising the steps of:
causing charged particles to pass through a track layer to form a multiplicity of charged-particle tracks therethrough;
creating corresponding open spaces through the track layer by a procedure that entails etching the track layer along the charged-particle tracks;
forming electron-emissive elements accessible through the open spaces in the track layer; and
providing a patterned electrically non-insulating gate layer over the electron-emissive elements such that gate openings extend through the gate layer to enable each gate opening to expose at least one of the electron-emissive elements.

18. A method as in Claim 17 wherein the forming step comprises forming the electron-emissive elements over a lower electrically non-insulating region provided below the track layer such that each electron-emissive element is electrically coupled to the lower non-insulating region through the corresponding open space in the track layer.

19. A method as in Claim 17 wherein the forming step comprises defining the electron-emissive elements in an electrically non-insulating emitter region provided below the track layer.

20. A method as in Claim 19 wherein the defining step comprises:
using the open spaces in the track layer to define corresponding cap regions over the emitter layer;
removing the track layer; and
removing (a) selected material of the emitter layer using the cap regions as masks to control the removal of the selected material such that
corresponding electron-emissive elements are defined in the remainder of the emitter layer at locations respectively centered on the cap regions and (b) the cap regions.

21. A method comprising the steps of:
causing charged particles to pass through an electrically insulating track layer to form a
multiplicity of charged-particle tracks therethrough;
creating corresponding open spaces through the track layer by a procedure that entails etching the track layer along the charged-particle tracks;
forming corresponding electron-emissive elements over a lower electrically non-insulating region provided below the track layer such that each electron-emissive element is electrically coupled to the lower non-insulating region through the corresponding open space in the track layer; and
providing a patterned electrically non-insulating gate layer over the track layer such that a like multiplicity of gate openings extend through the gate layer at locations respectively centered on the electron-emissive elements.

22. A method as in Claim 17 or 21 wherein:
the creating step entails creating the open spaces generally in the shape of pores respectively centered on the charged-particle tracks; and
the forming step entails introducing electrically conductive filament material into the pores to form the electron-emissive elements generally in the shape of filaments.

23. A method comprising the steps of:
causing charged particles to pass through a track layer to form a multiplicity of charged-particle tracks therethrough;
creating corresponding apertures through the track layer by a procedure that entails etching the track layer along the charged-particle tracks;
etching an underlying electrically non-insulating gate layer through the apertures in the track layer to form corresponding gate openings through the gate layer; and
etching an underlying electrically insulating layer through the gate openings to form corresponding dielectric open spaces substantially through the insulating layer down to locations for electron-emissive elements along an underlying lower
electrically non-insulating region.

24. A method as in Claim 23 further including the step of forming the electron-emissive elements over the lower non-insulating region such that the electron-emissive elements are electrically coupled to the lower non-insulating region, each dielectric space being provided with a corresponding one of the electron-emissive elements.

25. A method as in Claim 24 wherein the forming step entails depositing material through the gate openings in a manner centered on the gate openings to at least partially form the electron-emissive elements,

26. A method as in any of Claims 23 - 25 wherein each electron-emissive element comprises electrically non-insulating material generally in the shape of an electron-emissive cone that points away from the lower non-insulating region.

27. A method as in Claim 26 wherein each
electron-emissive element further includes an
electrically non-insulating pedestal situated between the lower non-insulating region and that element's cone.

28. A method as in any of Claims 23 - 27 wherein: charged particles also pass through the gate and insulating layers during the causing step such that each track is an upper segment of a composite charged-particle track that includes a lower segment which extends through the insulating layer in line with the upper track segment; and
the insulating layer is etched along the lower track segments.

29. A method as in Claim 23 further including the step of forming the electron-emissive elements over the lower non-insulating region such that the electron-emissive elements are electrically coupled to the lower non-insulating region, each dielectric open space being provided with a plurality of the electron-emissive elements.

30. A method as in Claim 23 further including the steps of:
distributing electron-emissive particles over the lower non-insulating region such that the particles are electrically coupled to it; and
removing part of the lower non-insulating region using the particles as masks to protect underlying material of the lower non-insulating region in order to form corresponding pedestals respectively below the particles, each electron-emissive element comprising one of the particles and the underlying one of the pedestals.

31. A method comprising the steps of:
creating a structure in which an electrically insulating layer lies over a lower electrically non-insulating region, an electrically non-insulating gate layer lies over the insulating layer, and a track layer lies over the gate layer;
causing charged particles to pass through the track layer to form a multiplicity of charged-particle tracks therethrough;
etching the track layer along the tracks to form corresponding apertures through the track layer;
etching the gate layer through the apertures in the track layer to form corresponding gate openings through the gate layer;
etching the insulating layer through the gate openings to form corresponding dielectric open spaces through the insulating layer; and
forming a like multiplicity of electron-emissive elements over the lower non-insulating region such that each electron-emissive element contacts the lower non-insulating region through a corresponding one of the dielectric open spaces.

32. A method as in Claim 31 wherein:
each dielectric open space is a pore; and
the forming step comprises introducing
electrically non-insulating filament material into the pores to form the electron-emissive elements as filaments.

33. A method as in Claim 32 further including the step of removing material of the insulating layer exposed through the gate openings to form cavities situated around the filaments so that the filaments extend outward beyond the remainder of the insulating layer, the cavities extending at least partway down to the lower non-insulating region.

34. A method as in Claim 31 wherein the forming step comprises:
introducing electrically non-insulating pedestal material into the dielectric open spaces to form corresponding pedestals therein; and
providing electrically non-insulating tip material on the upper ends of the pedestals to form
corresponding generally pointed electron-emissive tips pointing away from the lower non-insulating region.

35. A method as in Claim 34 wherein the forming step includes, between the introducing and providing steps, expanding the dielectric open spaces by removing portions of the insulating layer exposed through the gate openings to form corresponding cavities situated around the pedestals so that the pedestals extend outward beyond the remainder of the insulating layer, the cavities extending at least partway through the insulating layer.

36. A method as in Claim 31 wherein:
each dielectric open space comprises (a) a cavity extending partway through the insulating layer along its upper surface and (b) a corresponding pore
extending through the insulating layer at the bottom of the cavity, the pore being narrower than the cavity; and
the forming step comprises (a) introducing
electrically non-insulating pedestal material into the pores to form corresponding pedestals therein and (b) depositing electrically non-insulating cone material such that the cone material accumulates over the pedestals generally in the shape of corresponding electron-emissive cones pointing away from the lower non-insulating region.

37. A method as in Claim 31 wherein the forming step comprises depositing electrically non-insulating cone material into the dielectric open spaces such that the cone material accumulates over the lower non-insulating region generally in the shape of
corresponding electron-emissive cones pointing away from the lower non-insulating region.

38. A method as in any of Claims 31 - 37 wherein: charged particles also pass through the gate and insulating layers during the causing step such that each track is an upper segment of a composite charged-particle track that includes a lower segment which extends through the insulating layer in line with the upper track segment; and
the insulating layer is etched along the lower track segments.

39. A method as in any of Claims 31 - 38 wherein each electron-emissive element comprises (a) an
electrically resistive portion situated over the lower non-insulating region and (b) an electron-emissive portion situated over the resistive portion.

40. A method as in any of Claims 31 - 39 wherein the lower non-insulating region comprises an
electrically conductive part and an electrically resistive part situated over the conductive part.

41. A method comprising the steps of:
creating a structure in which a first electrically insulating layer lies over a lower electrically non-insulating region, an electrically non-insulating gate layer lies over the first insulating layer, a second electrically insulating layer lies over the gate layer, a second electrically non-insulating layer lies over the second insulating layer, and a track layer lies over the second non-insulating layer;
causing charged particles to pass through the five layers to form a multiplicity of charged-particle tracks down to the lower non-insulating region, each charged-particle track comprising (a) a first segment through the first insulating layer, (b) a second segment through the second insulating layer in line with the first segment, and (σ) a third segment through the track layer in line with the other two segments;
etching the track layer along the third track segments to form corresponding apertures through the track layer;
etching the second non-insulating layer through the apertures in the track layer to form corresponding openings through the second non-insulating layer;
etching the second insulating layer through the openings in the second non-insulating layer along the second track segments to form corresponding apertures through the second insulating layer;
etching the gate layer through the apertures in the second insulating layer to form corresponding gate openings through the gate layer;
etching the first insulating layer through the gate openings along the first track segments to form corresponding dielectric open spaces through the first insulating layer; and
forming, in the dielectric open spaces,
corresponding electron-emissive elements that contact the lower non-insulating region.

42. A method as in any of Claims 17 - 41 wherein the electron-emissive elements are operable in field-emission mode.

43. A method that comprises the following steps for manufacturing electrodes of an electronic device:
causing charged particles to pass through a track layer to form a multiplicity of charged-particle tracks therethrough;
creating corresponding apertures through the track layer by a procedure that entails etching the track layer along the charged-particle tracks;
etching an underlying electrically non-insulating layer through the apertures in the track layer to form corresponding openings through the non-insulating layer; and
etching an underlying electrically insulating layer through the openings in the non-insulating layer to form corresponding dielectric open spaces through the insulating layer down to an underlying lower electrically non-insulating region.

44. A method as in Claim 43 further including the steps of:
patterning at least part of the lower non-insulating region into a group of lower lines extending in a first direction; and
patterning at least part of the non-insulating layer into a group of lines extending above the lower lines in a second direction different from the first direction.

45. A structure comprising:
a substrate for providing structural support;
a patterned lower electrically non-insulating region comprising a group of generally parallel lines situated over electrically insulating material of the substrate;
an electrically insulating layer situated over the lower non-insulating region; and
a multiplicity of electron-emissive filaments respectively situated in corresponding pores extending through the insulating layer down to the lower non-insulating region, the lower end of each filament contacting the lower non-insulating region.

46. A structure as in Claim 45 wherein the filaments extend above the insulating layer.

47. A structure comprising:
a lower electrically non-insulating region which comprises an electrically conductive portion and an electrically resistive portion situated over the conductive portion;
an electrically insulating layer situated over the resistive portion; and
a multiplicity of electron-emissive filaments respectively situated in corresponding pores extending through the insulating layer down to the lower non-insulating region, the lower end of each filament contacting the resistive portion.

48. A structure as in Claim 47 wherein the lower non-insulating region is a patterned layer comprising a group of generally parallel lines, each formed with segments of both portions of the lower non-insulating region.

49. A structure as in any of Claims 45 - 48 further including a patterned electrically non-insulating gate layer situated over the insulating layer, gate openings which respectively correspond to the filaments being provided through the gate layer at locations generally centered on the filaments such that the filaments are separated from the gate layer.

50. A structure comprising:
a substrate for providing structural support;
a lower electrically non-insulating region situated over electrically insulating material of the substrate;
an electrically insulating layer situated over the lower non-insulating region;
a multiplicity of electron-emissive filaments respectively situated in corresponding pores extending through the insulating layer down to the lower non-insulating region, the lower end of each filament contacting the lower non-insulating region; and
a patterned electrically non-insulating gate layer situated over the insulating layer, gate openings which respectively correspond to the filaments being provided through the gate layer at locations generally centered on the filaments such that the filaments are separated from the gate layer.

51. A structure as in any of Claims 49 - 51 wherein cavities which respectively correspond to the filaments are provided in the insulating layer along its upper surface at locations generally centered on the filaments, the cavities extending downward partway through the insulating layer, each cavity being wider than the corresponding pore so that each filament protrudes from its pore into the corresponding cavity.

52. A structure as in any of Claims 49 - 51 further including:
a second electrically insulating layer situated over the gate layer; and
a second electrically non-insulating layer situated over the second insulating layer, openings which respectively correspond to the filaments being provided through both second layers at locations generally centered on, and situated above, the
filaments.

53. A structure comprising:
a lower electrically non-insulating metal region; and
a multiplicity of laterally separated electron-emissive elements contacting the lower non-insulating region, each electron-emissive element comprising (a) an electrically resistive portion situated over the lower non-insulating region and (b) a corresponding electron-emissive portion situated over the resistive portion.

54. A structure as in Claim 53 wherein the electron-emissive portion of each electron-emissive element comprises a generally pointed tip pointing away from the lower non-insulating region.

55. A structure as in Claim 53 wherein the electron-emissive portion of each electron-emissive element comprises material generally in the shape of a cone pointing away from the lower non-insulating region, the diameter of the cone at its base being greater than the maximum diameter of the underlying resistive portion.

56. A structure as in Claim 53 wherein each electron-emissive element is generally in the shape of a cone pointing away from the lower non-insulating region.

57. A structure comprising:
a lower electrically non-insulating region;
a multiplicity of laterally separated electron-emissive elements, each comprising (a) an electrically non-insulating pedestal situated over the lower non-insulating region and (b) an electron-emissive portion situated over the pedestal, the electron-emissive portion being generally in the shape of a cone that points away from the lower non-insulating region, the diameter of the cone at its base being greater than the maximum diameter of the pedestal.

58. A structure as in Claim 57 wherein the lower non-insulating region comprises (a) an electrically conductive part and (b) an electrically resistive part situated over the conductive part, the pedestals situated on the resistive part.

59. A structure as in any of Claims 53 - 58 further including:
an electrically insulating layer lying over the lower non-insulating region, a like multiplicity of dielectric open spaces extending fully through the insulating layer, at least part of each electron-emissive element situated in a corresponding one of the dielectric open spaces; and
a patterned electrically non-insulating gate layer lying over the insulating layer, a like multiplicity of gate openings extending fully through the gate layer, each electron-emissive element being exposed through a corresponding one of the gate openings.

60. A structure as in any of Claims 53 - 59 wherein the electron-emissive elements are operable in field-emission mode.

_
receive tø the .International Bureau on 28 February 1995 (28.02.95); "^cigάnal' Laim.-l amended; remaining claims unchanged (1 page)
1. A method comprising the steps of:
creating a structure in which an electrically
insulating layer lies over a patterned lower
electrically non-insulating region comprising a group of generally parallel lines situated over electrically insulating material of a substrate, a multiplicity of pores extending through the insulating layer down to the lower non-insulating region; and
introducing electrically non-insulating filament material into the pores to form respectively
corresponding electron-emissive filaments therein, the lower end of each filament contacting the lower non- insulating region.

2. A method as in Claim 1 further including the step of sharpening the upper ends of the filaments to form sharpened tips.

3. A method comprising the steps of:
creating a structure in which an electrically
insulating layer lies over an electrically resistive portion of a lower electrically non-insulating region that also includes an electrically conductive portion situated under the resistive portion, a multiplicity of pores extending through the insulating layer down to the resistive portion; and
introducing electrically non-insulating filament material into the pores to form corresponding electron- emissive filaments therein, the lower end of each
filament contacting the resistive portion.

4. A method as in Claim 3 wherein the lower non- insulating region is a patterned layer comprising a group of generally parallel lines, each being formed with segments of both portions of the lower non- insulating region.
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AMENDED SHEET (ARTICLE 18)