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1. (WO2016203193) UNITÉ DE GÉNÉRATION D'ÉVÉNEMENT
Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

Claims

1. A microcontroller comprising:

a processor;

a plurality of peripherals;

a programmable peripheral interconnect;

an event-generating unit; and

a memory, storing software,

wherein:

the event-generating unit comprises an event-generating register, addressable by the processor;

the event-generating unit is connected to the programmable peripheral interconnect; and

the event-generating unit is arranged to detect a predetermined change to the contents of the event-generating register and, in response to detecting such a predetermined change, to signal an event to the programmable peripheral interconnect;

each of the peripherals is connected to the programmable peripheral interconnect;

each of the peripherals is configured to respond to a task signal from the programmable peripheral interconnect by performing a respective task;

the programmable peripheral interconnect is configured to access a mapping memory in which a plurality of mappings can be stored, each mapping an event of the event-generating unit to a task of one of the peripherals;

the programmable peripheral interconnect is configured so that, when a mapping is stored in the mapping memory from an event of the event-generating unit to a task of one of the peripherals, the programmable peripheral interconnect will respond to a signal of the event from the event-generating unit by sending a task signal to the peripheral;

the programmable peripheral interconnect is configured so that, when the mapping memory stores mappings from one event of the event-generating unit to two or more different tasks, the programmable peripheral interconnect will send the two or more respective task signals within a predetermined maximum time from receiving a signal of the event; and

the software comprises instructions, executable by the processor, to (i) store, in the mapping memory, mappings from one event of the event-generating unit to at least two different peripheral tasks, and (ii) make said predetermined change to the contents of the event-generating register.

2. A microcontroller as claimed in claim 1 , wherein the predetermined maximum time is 10 microseconds or less.

3. A microcontroller as claimed in claim 1 or 2, wherein the programmable peripheral interconnect is arranged to send the two or more respective task signals simultaneously.

4. A microcontroller as claimed in claim 3, wherein there is a constant time delay between the programmable peripheral interface receiving a signal of an event and sending two or more task signals that are mapped to the event, for all possible mappings,

5. A microcontroller as claimed in any preceding claim, comprising one or more peripherals that are event-generating, being configured to signal an event to the programmable peripheral interconnect, wherein the programmable peripheral interconnect is arranged so that, when a mapping is stored in the mapping memory between an event of a first peripheral and a task of a second peripheral, the programmable peripheral interconnect will provide a channel by sending a task signal to the second peripheral in response to a signal of the event from the first peripheral.

6. A microcontroller as claimed in any preceding claim, wherein the event-generating unit is arranged to signal a plurality of different events.

7. A microcontroller as claimed in claim 6, wherein the event-generating unit has a plurality of event-generating registers, addressable by the processor, wherein each event-generating register is associated with a different respective event.

8. A microcontroller as claimed in any preceding claim, wherein the event-generating unit is able to receive a task signal from the programmable peripheral interconnect.

9. A microcontroller as claimed in any preceding claim, wherein the

programmable peripheral interface is connected to the peripherals and to the event-generating unit by respective lines for each event and task.

10. A microcontroller as claimed in any preceding claim, wherein the

programmable peripheral interface comprises at least one event register, addressable by the processor, associated with an event of the event-generating unit.

11. A microcontroller as claimed in claim 10, wherein the event register is separate from the event-generating register and wherein the event-generating unit is configured so that a predetermined change to the contents of the event-generating register will cause a predetermined change to the contents of the event register.

12. A microcontroller as claimed in any preceding claim, wherein the event-generating unit comprises a plurality of event-generating registers and a plurality of event registers, wherein each event-generating register is associated with a respective one of the event registers, such that a change to one of the event-generating registers causes a change to an associated one of the event registers.

13. A microcontroller as claimed in claim 10, wherein the event-generating register is the event register.

14. A microcontroller as claimed in any preceding claim, wherein the event-generating unit has no outputs other than one or more event lines to the PPI; zero or more interrupt lines to the processor; and zero or more registers.

15. A microcontroller as claimed in any preceding claim, wherein the event-generating unit has no inputs other than a clock input, one or more registers, and zero or more task lines.

16. A microcontroller as claimed in any preceding claim, comprising circuitry for sending an interrupt to the processor when signalling an event.

17. A microcontroller as claimed in any preceding claim, comprising a plurality of event-generating units, each connected to the processor by a set of interrupt lines, each set of interrupt lines having a different respective interrupt priority level.

18. A microcontroller comprising:

a processor;

a plurality of peripherals;

a programmable peripheral interconnect; and

an interrupt-generating unit,

wherein:

an event-generating one of the peripherals is configured to signal an event to the programmable peripheral interconnect;

the interrupt-generating unit is arranged to send an interrupt to the processor in response to receiving a task signal from the programmable peripheral interconnect; the programmable peripheral interconnect is configured to access a memory in which a mapping can be stored between (i) an event of a first peripheral and (ii) a task of the interrupt-generating unit or of a second peripheral; and

the programmable peripheral interconnect is configured so that, when a mapping is stored in memory between an event of a first peripheral and a task of the interrupt-generating unit, the programmable peripheral interconnect will respond to a signal of the event from the first peripheral by sending a task signal for the task to the interrupt-generating unit.

19. A microcontroller as claimed in claim 18, wherein the interrupt-generating unit is also an event-generating unit, arranged to detect a predetermined change to the contents of an event-generating register and, in response to detecting such a predetermined change, to signal an event to the programmable peripheral

interconnect.

20. A microcontroller as claimed in claim 18 or 19, wherein the interrupt-generating unit is arranged to send the interrupt within a predetermined maximum from receiving the task signal.

21. A microcontroller as claimed in any of claims 18 to 20, wherein the interrupt-generating unit is arranged to send the interrupt at a constant time delay after receiving the task signal.

22. A microcontroller as claimed in any of claims 18 to 21 , comprising a plurality of interrupt-generating units, each connected to the processor by a set of interrupt lines, each set of interrupt lines having a different respective interrupt priority level.

23. A microcontroller as claimed in any of claims 18 to 22, comprising a memory storing software, the software comprising instructions, executable by the processor, to store, in the mapping memory, a mapping from an event of the event-generating peripheral to a task of the interrupt-generating unit.