Traitement en cours

Veuillez attendre...

Paramétrages

Paramétrages

Aller à Demande

1. WO2003025937 - FONCTIONNEMENT EN ARRIERE-PLAN POUR CELLULES MEMOIRES

Note: Texte fondé sur des processus automatiques de reconnaissance optique de caractères. Seule la version PDF a une valeur juridique

[ EN ]

WHAT TS CLAIMED IS:

1. A method of operating an integrated circuit with nonvolatile memory cells comprising:
turning on a charge pump to generate an erase voltage;
charging one or more erase gates of nonvolatile memory cells selected for erase to the erase voltage;
turning off the charge pump;
allowing the erase gates to hold the erase voltage dynamically while the charge pump is off; and
erasing the selected nonvolatile memory cells using the dynamic erase voltage.

2. The method of claim 1 further comprising:
periodically turning on the charge pump to refresh the erase voltage on the erase gates.

3. The method of claim 1 further comprising:
permitting programming of nonvolatile memory cells, other than the nonvolatile memory cells selected for erase, while the charge pump is off.

4. The method of claim 2 further comprising:
permitting reading of nonvolatile memory cells, other than the nonvolatile memory cells selected for erase, while the charge pump is off.

5. The method of claim 1 wherein each nonvolatile memory cell comprises two floating gate transistors and one select transistor having an erase gate.

6. The method of claim 1 wherein the erase voltage is a voltage in a range from about 15 volts to about 22 volts.

7. The method of claim 1 further comprising:
checking whether the selected nonvolatile memory cells are erased; and
if the selected nonvolatile memory cells are not erased, turning on the charge pump to refresh the erase voltage on the erase gates.

8. The method of claim 1 further comprising:
permitting other operations within the integrated circuit, other than operations on the nonvolatile memory cells selected for erase, while the charge pump is off.

9. The method of claim 7 further comprising:
after the selected nonvolatile memory cells are erased, discharging the erase voltage from the erase gates.

10. A method of operating an integrated circuit comprising:
erasing selected memory cells by dynamically charging erase gates of the selected memory cells by periodically directly applying an erase voltage to the erase gates;
permitting operations on memory cells, other than the selected memory cells, when the erase voltage is not being directly applied to the erase gates; and
when the selected memory cells are erased, discharging the erase gates of the selected memory cells to a voltage level below the erase voltage.

11. The method of claim 10 wherein the selected memory cells are erased when a NT of a floating gate transistor becomes about 6 volts or above.

12. The method of claim 10 wherein all the memory cells of the integrated circuit may be selected for erase by dynamically charging all erase gates of the memory cells.

13. The method of claim 11 wherein each memory cell comprises a floating gate transistor.

14. The method of claim 11 wherein each memory cell comprises a multibit floating gate transistor.

15. An integrated circuit comprising:
an array of memory cells arranged in rows and columns;
a plurality of transfer transistors, each coupled to a row of the array of memory cells; and
a plurality of erase pumps, each coupled to one of the transfer transistors, wherein an erase pump dynamically charges erase gates of a row of memory cells to an erase voltage through a respective transfer transistor and the erase voltage is dynamically held at the erase gates by turning off the respective transfer transistor.

16. The integrated circuit of claim 15 wherein each memory cell comprises:
a first floating gate transistor with a first control gate;
a second floating gate transistor with a second control gate; and
a select transistor, coupled between the first and second floating gate transistors, wherein the select transistor has an erase gate.

17. A method of operating an integrated circuit with nonvolatile memory having a controlled gate acting upon memory cells comprising:
turning on a circuit to generate an operating voltage;
charging one or more gates of nonvolatile memory cells selected for operation to the operating voltage;
disconnecting the circuit if it is not needed;
allowing the disconnected gates to hold the voltage dynamically while the circuit is off; and
operating the selected nonvolatile memory cells using the dynamic voltage.

18. The method of claim 17 further comprising:
periodically turning on the circuit if it was turned off and reconnecting to the previously selected gates, not actively discharged.

19. The method of claim 17 further comprising:
permitting programming of nonvolatile memory cells, other than the nonvolatile memory cells selected for erase, while the charge pump is not connected to previously selected erase gates.

20. The method of claim 17 further comprising:
permitting reading of nonvolatile memory cells, other than the nonvolatile memory cells selected for erase, while the charge pump is not connected to previously selected erase gates.

21. The method of claim 17 further comprising:
assessing whether the specified operation is accomplished; and
if the specified operation on selected nonvolatile memory cells has not been accomplished, connecting the charge pump to refresh the operating voltage on the gates.

22. A method of operating an integrated circuit comprising:
connecting an operating voltage to a first portion of nonvolatile memory cells;
charging a node of the first portion of nonvolatile memory cells to the operating voltage;
disconnecting the operating voltage from the node of the first portion of the memory cells;
permitting the node of the first portion of nonvolatile memory cells to hold the operating voltage dynamically;
operating on the first portion of nonvolatile memory cells dynamically.

23. The method of claim 22 further comprising:
while the first portion of nonvolatile memory cells is dynamically being operated on, permitting operation on a second portion of nonvolatile memory cells.