We claim:

1. A coordinate transformation circuit for converting digital chrominance signals of a first cartesian color coordinate system into digital hue signals and saturation signals of a polar color coordinate system, whereby a second cartesian color coordinate system (8) with axes parallel to the first cartesian color coordinate system (1) is placed through the center point (P'
_{o}) of the polar color coordinate system (4), said second cartesian color coordinate system (8) dividing the polar color coordinate system (4) into four quadrants, which are defined by digital quadrant identification numbers, comprising:

a. means for converting the pairs of digital chrominance signal values (X; Y), defining the positions of the color locations (F) within the first cartesian color coordinate system (1) into corresponding pairs of second chrominance signal values (X'; Y'), defining the relative positions of said color locations (F) within a selected quadrant of the second cartesian color coordinate system (8),

b. means for generating digital hue signal values (T*) for said selected quadrant and saturation signal values (S) from said pairs of second chrominance signal values (X'; Y') according to the equations:

T*=C
_{2} arc tan (Y'/X') and

S=C
_{1} √X'
^{2} +Y'
^{2}

wherein C
_{1} and C
_{2} are constant factors, and

c. means for determining the quadrant identification numbers of the quadrants, in which the respective color locations (F) fall, from said first chrominance signal values (X; Y), whereby the hue signal values (T) for all quadrants are obtained from said determined quadrant identification numbers and said hue signal values (T*) of said selected quadrant.

2. A coordinate transformation circuit according to claim 1, comprising allocating increasing digital quadrant identification numbers to the individual quadrants in the direction of increasing tint signals (T); and in that the marked quadrant identification numbers respectively form the most significant bits of the tint signals (T) to be determined for all quadrants and the tint signals (T*) of the quadrant respectively form the least significant bits of the tint signals (T) to be determined for all quadrants.

3. A coordinate transformation circuit according to claim 2, characterized in that the coordinates of the center point (P'
_{o}) and of the maximum radius of the polar color coordinate system (4) correspond to half the final values of the digital chrominance signals (X;Y) in the first cartesian color coordinate system (1).

4. A coordinate transformation circuit according to claim 1, characterized in that the digital quadrant identification numbers are determined from a logical linkage of the respective most significant bits (MSB) of the digital chrominance signals (X;Y).

5. A coordinate transformation circuit according to claim 1, characterized in that the digital coordinate values X'(Y') are obtained by omission of the most significant bits (MSB) and inversion of all least significant bits (LSB) of the digital chrominance signals X(Y) in case when the appertaining chrominance signals X(Y) lie to the left of the Y' axis (below the X' axis) of the second cartesion color coordinate system (8); and in that the digital coordinate values X'(Y') are obtained by omission of the most significant bits (MSB) and non-inversion of all least significant bits (LSB) of the digital chrominance signals X(Y) in case when the appertaining chrominance signals X(Y) lie to the right to the Y' axis (above the X' axis) of the second color coordinate system (8).

6. A coordinate transformation circuit according to claim 5, characterized in that the inversion or non-inversion of all least significant bits of the chrominance signals X and Y is controlled by the respective most significant bit.

7. A coordinate transformation circuit according to claim 1, characterized in that the functions:

S=c
_{1} √X'
^{2} +y'
^{2}

and

T*-c
_{2} ·arc tan Y'/X'

are stored for one of the quadrants in a table memory which is addressed by the digital coordinate values X' and Y'.

8. A coordinate transformation circuit according to claim 1, characterized in that the digital tint signals (T) are inverted in case they fall in the second or fourth quadrants.

9. A coordinate transformation circuit according to claim 8, characterized in that the inversion of the digital tint signals (T) is controlled as a function of the quadrant identification numbers.

10. A coordinate transformation circuit according to claim 9, characterized in that the digital coordinate values (X';Y') are subjected to a place shift before the addressing of the table memory; and the place shift is again reversed for the values read out of the table memory.

11. A coordinate transformation circuit according to claim 10, characterized in that the number of places by which the coordinate values X' and Y' are shifted depends on the value of the appertaining coordinate values X' and Y'.

12. A coordinate transformation circuit according to claim 10, characterized in that the coordinate values X' and Y' are subdivided into value ranges and a corresponding place shift is undertaken for each value range.

13. A coordinate transformation circuit for converting digital chrominance signals of a cartesian color coordinate system into digital hue signals and saturation signals of a polar color coordinate system, whereby a second cartesian color coordinate system (8) with axes parallel to the first cartesian color coordinate system (1) is placed through the center point (P
_{o} ') of the polar color coordinate system (4), said second cartesian color coordinate system (8) dividing the polar color coordinate system (4) into four quadrants, which are defined by digital quadrant identification numbers, comprising:

a. a table memory (12; 12') for storing digital hue signal values (T*) and saturation signal values (S) calculated from second chrominance signals (X'; Y') of a selected quadrant of the second cartesian color coordinate system (8) according to the equations:

T*=C
_{2} arc tan Y'/X' and

S=C
_{1} √X'
^{2} +Y'
^{2}

wherein C
_{1} and C
_{2} are constant factors said saturation signal values (S) and said hue signal values (T*) being addressable by said corresponding chrominance signal values (X'; Y'), said table memory (12; 12') having address-inputs and respective hue signal value outputs (37) and saturation signal value outputs (38),

b. an inversion stage (10) connected to the address-inputs of the table memory (12; 12') and supplied with the first digital chrominance signals (X, Y) of the first cartesian color coordinate system (1) for inverting each pair of the supplied first digital chrominance signal values (X; Y) into a corresponding pair of second chrominance signal values (X'; Y) of the second cartesian color coordinate system within said selected quadrant; said second chrominance signal values (X'; Y') representing the addresses for said table memory (12; 12'),

c. a quadrant recognition stage (11) supplied with the most significant bits (MSB) of said first digital chrominance signal values (X; Y) for recognizing the digital quadrant identification number of the quadrant in which each pair of first chrominance signal values (X; Y) falls at outputs of the quadrant recognition stage (11); and

d. an inverter-stage (13) connected to the hue signal value outputs (37) of the table memory (12; 12') and to the outputs of the quadrant recognition stage (11), said inverter-stage (13), being controlled by said quadrant recognition stage (11), inverting or not inverting the hue signal values (T*) in dependence of the recognized digital quadrant identification numbers, whereby the digital quadrant identification numbers represent the most significant bits (MSB) and the inverted or not inverted hue signal values (T*) of the selected quadrant the least significant bits (LSB) of the digital hue signal values of the polar color coordinate system (4).

14. A coordinate transformation circuit according to claim 13, wherein the inversion stage (10) consists of inverters for the least significant bits (LSB) of the first chrominance signal values (X; Y) which are controlled by the respective most significant bits (MSB) of said first chrominance signal values (X; Y).

15. A coordinate transformation circuit according to claim 13, further comprising: a shift stage (46), connected to the outputs of the inversion stage (10) and to the address-inputs of the table memory (12') for shifting the addresses of the table memory (12') in dependence of the second chrominance signal values (X'; Y), a correction stage (52) connected to the saturation signal value-outputs (38) of the table memory (12') for correcting the saturation signal values incorrectly read from the table memory (12') by said shifted addresses; and a control generator (48) connected to said shift stage (46) and to said correction stage (52) and being supplied with said second chrominance signal values (X'; Y') for controlling the shifting- and correction process in dependence of the second chrominance signal values (X'; Y').