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1. (WO2019066960) STACKED DIE SEMICONDUCTOR PACKAGE SPACER DIE
Nota: Texto obtenido mediante procedimiento automático de reconocimiento óptico de caracteres.
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WHAT IS CLAIMED:

1. A semiconductor package comprising:

a substrate having an upper surface, a transversely opposed second surface, and a substrate footprint area and a contact pad array disposed on the second surface of the substrate;

wherein the contact pad array includes a plurality of contact pads arranged in a first pattern; and

wherein the first pattern includes a plurality of peripheral contact pads;

a first die stack having a first die stack footprint area; the first die stack footprint area less than the substrate footprint area; and

a spacer die disposed between the upper surface of the substrate and first die stack the spacer die having a footprint area that is greater than the first die stack footprint area and the same or smaller than the substrate footprint area;

wherein the first die stack communicably couples to the upper surface of the spacer die in a location such that the first die stack footprint area partially shadows a portion of the plurality of peripheral contact pads; and

wherein the spacer die footprint area completely shadows the portion of the plurality of peripheral contact pads at least partially shadowed by the first die stack footprint.

2. The semiconductor package of claim 1, further comprising:

a plurality of solder balls, each of the plurality of solder balls conductively coupled to a respective one of the plurality of contact pads.

3. The semiconductor package of claim 1, further comprising:

an encapsulant disposed about at least a portion of the first die stack.

4. The semiconductor package of claim 1, further comprising:

a second die stack having a second die stack footprint area;

wherein a combined footprint area of the first die stack and the second die stack is less than the substrate footprint area;

wherein the first die stack and the second die stack footprint are spaced apart to provide an interstitial space between the first die stack footprint and the second die stack footprint;

wherein at least some of the plurality contact pads are disposed on the second surface of the substrate in the interstitial space between the first die stack footprint and the second die stack footprint such that the contact pads disposed in the interstitial space are partially shadowed by at least one of: the first die stack footprint or the second die stack footprint;

wherein the spacer die is disposed between the upper surface of the substrate and the first and the second die stacks; and

wherein the spacer die footprint area completely shadows the portion of the plurality of peripheral contact pads at least partially shadowed by the first die stack footprint and the contact pads disposed in the interstitial space between the first die stack and the second die stack.

5. The semiconductor package of claim 4:

wherein the second die stack communicably couples to the upper surface of the spacer die in a location such that the second die stack footprint partially shadows a portion of the plurality of peripheral contact pads;

wherein the spacer die footprint area completely shadows the portion of the plurality of peripheral contact pads at least partially shadowed by the footprint of the second die stack.

6. The semiconductor package of claim 4 wherein the first die stack and the second die stack comprise a system on a chip (SoC).

7. The semiconductor package of any of claims 1 through 6 wherein the spacer die comprises a silicon spacer die.

8. The semiconductor package of claim 7 wherein the silicon spacer die comprises a silicon-containing material having a thickness of from about 10 micrometers (μιη) to ΙΟΟμιη.

9. The semiconductor package of any of claims 1 through 6, further comprising a die attach film disposed between the first die stack and the spacer die;

wherein the die attach film comprises a material having a first modulus of elasticity; wherein the spacer die comprises a material having a second modulus of elasticity; and wherein a difference between the first modulus of elasticity and the second modulus of elasticity is less than 10% of the larger of the first modulus of elasticity or the second modulus of elasticity.

10. A semiconductor package fabrication method, comprising:

disposing a spacer die between a first die stack and a first surface of a substrate such that a first die stack footprint partially shadows a portion of each of a plurality of contact pads disposed on a second surface of the substrate;

coupling the first die stack to a first side of the spacer die, the spacer die having a footprint that is greater than the first die stack footprint; and

coupling the substrate to a second side of the spacer die, the second side of the spacer die transversely opposed to the first side of the spacer die, the spacer die having a footprint that is the same or smaller than the substrate footprint, the spacer die footprint shadowing the plurality of contact pads at least partially shadowed by the footprint of the first die stack.

11. The method of claim 10, further comprising:

conductively coupling each of a plurality of solder balls to a respective one of the plurality of contact pads.

12. The method of claim 10, further comprising:

disposing an encapsulant about at least a portion of the first die stack.

13. The method of claim 10, further comprising:

coupling a second die stack having a second die stack footprint area to the first side of the spacer die;

wherein a combined footprint area of the first die stack and the second die stack is less than the substrate footprint area;

wherein the first die stack and the second die stack footprint are spaced apart to provide an interstitial space between the first die stack footprint and the second die stack footprint;

wherein at least some of the plurality contact pads are disposed on the second surface of the substrate in the interstitial space between the first die stack footprint and the second die stack footprint such that the contact pads disposed in the interstitial space are partially shadowed by at least one of: the first die stack footprint or the second die stack footprint;

wherein the spacer die is disposed between the upper surface of the substrate and the first and the second die stacks; and

wherein the spacer die footprint area completely shadows the portion of the plurality of peripheral contact pads at least partially shadowed by the first die stack footprint and the contact pads disposed in the interstitial space between the first die stack and the second die stack.

14. The method of claim 13 wherein coupling a second die stack having a second die stack footprint area to the spacer die comprises:

coupling the second die stack to the spacer die in a location such that the second die stack footprint partially shadows a portion of the plurality of contact pads disposed about a periphery of the plurality of contact pads;

wherein the spacer die footprint area completely shadows the portion of the plurality of peripheral contact pads at least partially shadowed by the footprint of the second die stack.

15. The method of claim 14 wherein coupling the first die stack to a first side of the spacer die and the second die stack having a second die stack footprint area to the spacer die comprises:

coupling a system on a chip (SoC) that includes the first die stack and the second die stack to the first side of the spacer die.

16. The method of any of claims 10 through 15 wherein disposing a spacer die between a first die stack and a first surface of a substrate comprises:

disposing a spacer die comprising a silicon spacer die between a first die stack and a first surface of a substrate.

17. The method of claim 16 wherein disposing a spacer die comprising a silicon spacer die between a first die stack and a first surface of a substrate comprises:

disposing a spacer die that includes a silicon-containing material having a thickness of from about 10 micrometers (μιη) to ΙΟΟμιη between the first die stack and the first surface of the substrate.

18. The method of any of claims 10 through 15:

wherein coupling the first die stack to a first side of the spacer die further comprises: coupling the first die stack to a first side of the spacer die using die attach film disposed between the first die stack and the spacer die;

wherein the die attach film comprises a material having a first modulus of elasticity; and

wherein disposing a spacer die between a first die stack and a first surface of a substrate comprises:

disposing a spacer die that includes a material having a second modulus of elasticity between a first die stack and a first surface of a substrate wherein the spacer die;

wherein a difference between the first modulus of elasticity and the second modulus of elasticity is less than 10% of the larger of the first modulus of elasticity or the second modulus of elasticity.

19. A semiconductor package fabrication system, comprising:

means for disposing a spacer die between a first die stack and a first surface of a substrate such that a first die stack footprint partially shadows a portion of each of a plurality of contact pads disposed on a second surface of the substrate;

means for coupling the first die stack to a first side of the spacer die, the spacer die having a footprint that is greater than the first die stack footprint; and

means for coupling the substrate to a second side of the spacer die, the second side of the spacer die transversely opposed to the first side of the spacer die, the spacer die having a footprint that is the same or smaller than the substrate footprint, the spacer die footprint shadowing the plurality of contact pads at least partially shadowed by the footprint of the first die stack.

20. The system of claim 19, further comprising:

means for conductively coupling each of a plurality of solder balls to a respective one of the plurality of contact pads.

21. The system of claim 19, further comprising:

means for disposing an encapsulant about at least a portion of the first die stack.

22. The system of claim 19, further comprising:

means for coupling a second die stack having a second die stack footprint area to the first side of the spacer die;

wherein a combined footprint area of the first die stack and the second die stack is less than the substrate footprint area;

wherein the first die stack and the second die stack footprint are spaced apart to provide an interstitial space between the first die stack footprint and the second die stack footprint;

wherein at least some of the plurality contact pads are disposed on the second surface of the substrate in the interstitial space between the first die stack footprint and the second die stack footprint such that the contact pads disposed in the interstitial space are partially shadowed by at least one of: the first die stack footprint or the second die stack footprint;

wherein the spacer die is disposed between the upper surface of the substrate and the first and the second die stacks; and

wherein the spacer die footprint area completely shadows the portion of the plurality of peripheral contact pads at least partially shadowed by the first die stack footprint and the contact pads disposed in the interstitial space between the first die stack and the second die stack.

23. The system of claim 22 wherein the means for coupling a second die stack having a second die stack footprint area to the spacer die comprises:

means for coupling the second die stack to the spacer die in a location such that the second die stack footprint partially shadows a portion of the plurality of contact pads disposed about a periphery of the plurality of contact pads;

wherein the spacer die footprint area completely shadows the portion of the plurality of peripheral contact pads at least partially shadowed by the footprint of the second die stack.

24. The system of claim 23 wherein the means for coupling the first die stack to a first side of the spacer die and the second die stack having a second die stack footprint area to the spacer die comprises:

means for coupling a system on a chip (SoC) that includes the first die stack and the second die stack to the first side of the spacer die.

25. The system of any of claims 19 through 24 wherein the means for disposing a spacer die between a first die stack and a first surface of a substrate comprises:

means for disposing a spacer die comprising a silicon spacer die between a first die stack and a first surface of a substrate.