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ALLNUM:JP2017022453

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Analysis

1 / 1
1.2017142799PROCESSOR AND METHOD
JP - 17.08.2017
Int.Class G06F 9/305
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
305Controlling the executing of logical operations
 Appl.No 2017022453 Applicant INTEL CORP Inventor ROGER ESPASA

PROBLEM TO BE SOLVED: To provide an apparatus and a method for performing a plurality of multiplication operations.

SOLUTION: A processor comprises: an instruction fetch unit 138 for fetching a double-multiplication instruction from a memory subsystem, the double-multiplication instruction having three source operand values; a decode unit 140 for decoding the double-multiplication instruction to generate at least one μop; and an execution unit 162 for executing the μop at a first time to multiply the first and the second of the three source operand values to generate a first intermediate result and to execute the μop at a second time to multiply the intermediate result with the third of the three source operand values to generate final result.

SELECTED DRAWING: Figure 1B

COPYRIGHT: (C)2017,JPO&INPIT

2.2017022453VIDEO SIGNAL TRANSMISSION DEVICE AND VIDEO SIGNAL RECEPTION DEVICE
JP - 26.01.2017
Int.Class H04L 1/00
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
1Arrangements for detecting or preventing errors in the information received
 Appl.No 2015136256 Applicant NIPPON HOSO KYOKAI Inventor NAKATOGAWA TAKESHI

PROBLEM TO BE SOLVED: To achieve the transmission of a large capacity video signal at low cost without performing complicated signal processing and to suppress an adverse effect on image quality due to the occurrence of errors.

SOLUTION: A video bit string separation unit 11 of a video signal transmission device 1-1 separates multiple pieces of bit data constituting video data, i.e. a video signal, according to the quality of transmission paths 30-1 to 30-N in accordance with a preset rule, and generates N (N systems of) bit strings so that bit data at an upper-level side corresponds to a high-quality transmission path, and bit data at a lower-level side corresponds to a low-quality transmission path. Packet conversion units 12-1 to 12-N convert the bit strings into packet signals with transmission frame structure suitable for communication methods of the corresponding transmission paths 30-1 to 30-N. Transmission path encoding units 13-1 to 13-N apply transmission path encoding suitable for the communication methods of the corresponding transmission paths 30-1 to 30-N to the packet signals.

SELECTED DRAWING: Figure 1

COPYRIGHT: (C)2017,JPO&INPIT

3.WO/2018/003560ELECTRONIC CONTROL DEVICE
WO - 04.01.2018
Int.Class G06F 11/30
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
30Monitoring
 Appl.No PCT/JP2017/022453 Applicant HITACHI AUTOMOTIVE SYSTEMS, LTD. Inventor MATSUBARA Masahiro
The present invention prevents the accumulation of error detection delays that arise in the process of control processing in an electronic control device equipped with a plurality of computation devices. This electronic control device is equipped with first through third computation devices. A third computation device monitoring unit activates a second computation device monitoring unit. Upon activation by the third computation device monitoring unit, the second computation device monitoring unit confirms whether or not the first computation device has output an error, and notifies the third computation device of the result.
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