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1 / 59,975
1.WO/2011/145666PULSE OUTPUT CIRCUIT, SHIFT REGISTER, AND DISPLAY DEVICE
WO - 24.11.2011
Int.Class H03K 19/0175
HELECTRICITY
03ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
0175Coupling arrangements; Interface arrangements
 Appl.No PCT/JP2011/061465 Applicant SEMICONDUCTOR ENERGY LABORATORY CO., LTD. Inventor AMANO, Seiko
In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a bath mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.
2.WO/2011/055620SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
WO - 12.05.2011
Int.Class H01L 29/786
HELECTRICITY
01ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H1060
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
786Thin-film transistors
 Appl.No PCT/JP2010/068105 Applicant SEMICONDUCTOR ENERGY LABORATORY CO., LTD. Inventor YAMAZAKI, Shunpei
An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.
3.WO/2010/004944LIGHT-EMITTING DEVICE AND ELECTRONIC DEVICE USING THE SAME
WO - 14.01.2010
Int.Class H05B 33/12
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
33Electroluminescent light sources
12Light sources with substantially two-dimensional radiating surfaces
 Appl.No PCT/JP2009/062253 Applicant SEMICONDUCTOR ENERGY LABORATORY CO., LTD. Inventor SEO, Satoshi
A lightweight flexible light-emitting device which is able to possess a curved display portion and display a full color image with high resolution and the manufacturing process thereof are disclosed. The light-emitting device comprises: a plastic substrate; an insulating layer with an adhesive interposed therebetween; a thin film transistor over the insulating layer; a protective insulating film over the thin film transistor; a color filter over the protective insulating film; and a white-emissive light-emitting element formed over and being in contact with the thin film transistor.
4.WO/2012/005541PORTABLE DISPLAY DEVICE
WO - 12.01.2012
Int.Class G06F 3/14
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
14Digital output to display device
 Appl.No PCT/KR2011/005017 Applicant KIM, Si-Han Inventor KIM, Si-Han
The present invention relates to a portable display device which includes at least two panel housings, and the panel housings are provided with respective displays, such that the displays are interconnected to form a single screen when the panel housings are unfolded. The entire screen of the display device can be displayed as being divided in a vertical or horizontal direction by the first display and the second display. The first display and the second display contact each other. The portable display device includes a first input device corresponding to the information outputted on the first display and a second input device corresponding to the information outputted on the second display. The first input device and the second input device also contact each other, such that the two input devices can be used as a single input device.
5.WO/2010/058746SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
WO - 27.05.2010
Int.Class H01L 29/786
HELECTRICITY
01ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H1060
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
786Thin-film transistors
 Appl.No PCT/JP2009/069407 Applicant SEMICONDUCTOR ENERGY LABORATORY CO., LTD. Inventor MIYAIRI, Hidekazu
As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.
6.WO/2011/034068LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF
WO - 24.03.2011
Int.Class G09F 9/30
GPHYSICS
09EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30in which the desired character or characters are formed by combining individual elements
 Appl.No PCT/JP2010/065887 Applicant SEMICONDUCTOR ENERGY LABORATORY CO., LTD. Inventor EGUCHI, Shingo
An object of the invention is to improve the reliability of a light-emitting device. Another object of the invention is to provide flexibility to a light-emitting device having a thin film transistor using an oxide semiconductor film. A light-emitting device has, over one flexible substrate, a driving circuit portion including a thin film transistor for a driving circuit and a pixel portion including a thin film transistor for a pixel. The thin film transistor for a driving circuit and the thin film transistor for a pixel are inverted staggered thin film transistors including an oxide semiconductor layer which is in contact with a part of an oxide insulating layer.
7.WO/2013/077686PHASED INFORMATION PROVIDING SYSTEM AND METHOD
WO - 30.05.2013
Int.Class G06F 3/01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
01Input arrangements or combined input and output arrangements for interaction between user and computer
 Appl.No PCT/KR2012/010021 Applicant KIM, Si-Han Inventor KIM, Si-Han
The present invention relates to a terminal comprising a display, a central processing device and an input device. When an operation instruction for a phase of discriminating phases is input on the display, the input device outputs the operation instruction for the phase and the central processing device recognizes the phase of the operation instruction for the phase and outputs information relevant to the phase to the display. Thus, information relevant to the information being displayed on the current screen can be effectively displayed on the screen of the display even without executing several screen switching instructions.
8.WO/1993/001545HIGH-PERFORMANCE RISC MICROPROCESSOR ARCHITECTURE
WO - 21.01.1993
Int.Class G06F 9/30
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
 Appl.No PCT/JP1992/000868 Applicant SEIKO EPSON CORPORATION Inventor NGUYEN, Le Trong
The high-performance, RISC core based microprocessor architecture permits concurrent execution of instructions obtained from memory through an instruction prefetch unit having multiple prefetch paths allowing for the main program instruction stream, a target conditional branch instruction stream and a procedural instruction stream. The target conditional branch prefetch path allows both possible instruction streams for a conditional branch instruction to be prefetched. The procedural instruction prefetch path allows a supplementary instruction stream to be accessed without clearing the main or target prefetch buffers. Each instruction set includes a plurality of fixed length instructions. An instruction FIFO is provided for buffering instruction sets in a plurality of instruction set buffers including a first buffer and a second buffer. An instruction execution unit including a register file and a plurality of functional units is provided with an instruction control unit capable of examining the instruction sets within the first and second buffers and scheduling any of the instructions for execution by available functional units. Multiple data paths between the functional units and the register file allow multiple independent accesses to the register file by the functional units as necessary for the execution of the respective instructions.
9.WO/2000/017058CONTAINER, INSULATING CONTAINER, AND DEVICES AND METHOD USED FOR MANUFACTURING THESE CONTAINERS
WO - 30.03.2000
Int.Class B31B 15/00
BPERFORMING OPERATIONS; TRANSPORTING
31MAKING ARTICLES OF PAPER, CARDBOARD OR MATERIAL WORKED IN A MANNER ANALOGOUS TO PAPER; WORKING PAPER, CARDBOARD OR MATERIAL WORKED IN A MANNER ANALOGOUS TO PAPER
BMAKING CONTAINERS OF PAPER, CARDBOARD OR MATERIAL WORKED IN A MANNER ANALOGOUS TO PAPER
15Machinery characterised by making covered or externally-reinforced boxes or cartons
 Appl.No PCT/JP1999/005076 Applicant DAI NIPPON PRINTING CO., LTD. Inventor MOCHIZUKI, Yoichi
An insulating container (10) comprising a cylindrical shell part (11) having an opened upper part, a bottom part (12) covering the bottom part of the shell part (11), and a sleeve (10B) inserted between a cup main body (10A) having an inner surface at least on which polyolefin resin layer is formed and the outer peripheral surface of the shell part (11) of the cup main body (10A) with a clearance provided between them, wherein ribs (13, 13') are formed on the cup main body (10A) in the direction that the ribs surround the shell part (11) of the cup main body (10A), and the cup main body (10A) is formed so that the outside diameter of the opening part at the upper end of the shell part (11) is larger than the height of the cup main body (10A), whereby a paper insulating container stable in shape and insulation, easy to handle, excellent in design, high in flexibility of printing expression, sanitary, and less in load on environment can be provided while it is formed nearly in china bowls or bowls.
10.WO/2012/079403DOPING METHOD, PN STRUCTURE, METHOD FOR FABRICATING SOLAR CELL, AND SOLAR CELL
WO - 21.06.2012
Int.Class H01L 31/18
HELECTRICITY
01ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H1060
31Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
 Appl.No PCT/CN2011/080101 Applicant KINGSTONE SEMICONDUCTOR COMPANY LTD. Inventor CHEN, John
Disclosed is a doping method, comprising: forming an N+ doped layer in a surface of an N-type substrate; forming a mask on the surface of the N-type substrate, wherein a region that is not covered by the mask is an open region; etching the N+ doped layer to completely remove the N+ doped layer under the open region and expose the N-type substrate; forming a P+ doped region in the N-type substrate under the open region through ion injection, wherein the P+ doped region does not contact a non-etched N+ doped layer; removing the mask to obtain a PN structure comprising the N+ doped region and the P+ doped region, wherein the non-etched N+ doped layer is the N+ doped region. Also disclosed are a PN structure, a solar cell, and a fabrication method therefor. Through the present invention, the process steps are simplified, the purchase of a photo-etching machine and the use of multiple mask templates are not required, the problem of calibration of the mask templates does not exist, and the fabrication cost of the PN structure and the solar cell is reduced.
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