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1. (US6122195) Method and apparatus for decreasing block write operation times performed on nonvolatile memory

Office : United States of America
Application Number: 09330278 Application Date: 11.06.1999
Publication Number: 6122195 Publication Date: 19.09.2000
Grant Number: 6122195 Grant Date: 19.09.2000
Publication Kind : A
IPC:
G06F 11/00
G11C 16/04
G11C 16/06
G06F 11/20
G11C 16/08
G06F 12/02
G11C 16/10
G06F 15/40
G06F 3/06
G11B 20/10
G11C 17/00
G11C 29/00
G11C 5/00
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
04
using variable threshold transistors, e.g. FAMOS
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
07
Responding to the occurrence of a fault, e.g. fault tolerance
16
Error detection or correction of the data by redundancy in hardware
20
using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
08
Address circuits; Decoders; Word-line control circuits
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
10
Programming or data input circuits
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
20
Design or construction of the computing part, adapted to a specific application
40
for information retrieval; for compiling abstracts; Database structures therefor
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
G PHYSICS
11
INFORMATION STORAGE
B
INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
20
Signal processing not specific to the method of recording or reproducing; Circuits therefor
10
Digital recording or reproducing
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
17
Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
29
Checking stores for correct operation; Testing stores during standby or offline operation
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
5
Details of stores covered by group G11C11/63
CPC:
G11C 16/102
G06F 3/0616
G06F 3/064
G06F 3/0679
G06F 11/1068
G06F 12/0246
G11C 8/12
G11C 16/08
Applicants: Lexar Media, Inc.
Inventors: Estakhri Petro
Iman Berhanu
Agents: Imam Maryam
Priority Data: 08831266 31.03.1997 US
09264340 08.03.1999 US
09283728 01.04.1999 US
Title: (EN) Method and apparatus for decreasing block write operation times performed on nonvolatile memory
Abstract: front page image
(EN)

In accordance with an embodiment of the present invention, a solid state storage system and method is disclosed for reducing the number of write operations when re-writing a block of information that has been previously written by a host. The system includes a controller coupled to a host and a nonvolatile memory unit for controlling reading and writing of information organized in sectors from and to the nonvolatile memory unit, as commanded by the host. The controller maintains mapping of the sector information in an LUT stored in volatile memory the contents of which are lost if power is lost. Through the use of an address value and flag information maintained within each of the blocks of the nonvolatile memory unit, a block is re-written using a different number of write operations in various alternative embodiments of the present invention. The flag information is indicative of the status of the block such that during power-up, the controller reads the address value and the flag information of a block and determines the status of the block and in accordance therewith finishes re-writing of the block, if necessary and updates the LUT accordingly.