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1. (US5953737) Method and apparatus for performing erase operations transparent to a solid state storage system

Office : United States of America
Application Number: 09111414 Application Date: 07.07.1998
Publication Number: 5953737 Publication Date: 14.09.1999
Grant Number: 5953737 Grant Date: 14.09.1999
Publication Kind : A
IPC:
G06F 12/02
G06F 12/12
G06F 12/00
G06F 3/06
G06F 3/08
G06F 11/10
G11C 16/02
G11C 16/08
G11C 16/10
G11C 29/00
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
08
in hierarchically structured memory systems, e.g. virtual memory systems
12
Replacement control
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
08
from or to individual record carriers, e.g. punched card
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
07
Responding to the occurrence of a fault, e.g. fault tolerance
08
Error detection or correction by redundancy in data representation, e.g. by using checking codes
10
Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
08
Address circuits; Decoders; Word-line control circuits
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
10
Programming or data input circuits
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
29
Checking stores for correct operation; Testing stores during standby or offline operation
CPC:
G11C 16/08
G06F 3/061
G06F 3/0613
G06F 3/064
G06F 3/0652
G06F 3/0679
G06F 11/1068
G06F 12/023
G06F 12/0246
G11C 16/102
G11C 29/765
G11C 29/82
Applicants: Lexar Media, Inc.
Inventors: Estakhri Petro
Iman Berhanu
Agents: Imam Maryam
Priority Data: 08831266 31.03.1997 US
Title: (EN) Method and apparatus for performing erase operations transparent to a solid state storage system
Abstract: front page image
(EN)

In a digital system having a host, a controller device and at least one nonvolatile memory integrated circuit, such as a flash memory chip, a method and apparatus is disclosed for storing digital information, provided by the host, in the nonvolatile memory under the direction of the controller in an efficient manner so as to significantly improve system performance. The nonvolatile memory is organized into sequentially-numbered blocks. Each nonvolatile integrated circuit is assigned a predetermined number of sequential blocks and when a free block is solicited for storage of digital information provided by the host, the nonvolatile integrated circuit rather than the entire nonvolatile memory is searched for the free block. When the information stored in a block is being updated by the host, the nonvolatile integrated circuit assigned to that block is excluded from the search for the free block. Moreover, the nonvolatile integrated circuit having the greatest number of free blocks is used for searching of the free block and storing of the host-provided information to allow for equal use of the nonvolatile integrated circuits.