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1. (US20170212858) System for switching between a single node PCIe mode and a multi-node PCIe mode

Office : United States of America
Application Number: 15007753 Application Date: 27.01.2016
Publication Number: 20170212858 Publication Date: 27.07.2017
Grant Number: 10210121 Grant Date: 19.02.2019
Publication Kind : B2
IPC:
G06F 13/42
G06F 13/40
G06F 12/02
G06F 13/28
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38
Information transfer, e.g. on bus
42
Bus transfer protocol, e.g. handshake; Synchronisation
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38
Information transfer, e.g. on bus
40
Bus structure
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
20
for access to input/output bus
28
using burst mode transfer, e.g. direct memory access, cycle steal
CPC:
G06F 12/0246
G06F 13/287
G06F 13/4022
G06F 13/4282
G06F 2212/7208
Applicants: Quanta Computer Inc.
Inventors: Wei-Yi Chu
Chia-Feng Cheng
Kai Chang
Chih-Yu Chen
Agents: Nixon Peabody LLP
Zhou Lu
Priority Data:
Title: (EN) System for switching between a single node PCIe mode and a multi-node PCIe mode
Abstract: front page image
(EN)

A system for switching between a high performance mode and dual path mode is disclosed. The system includes a first device, a second device, a third device, and a switch configured to receive control signals, and in response causing the switch to selectively couple one or more first lanes of the first device or one or more second lanes of the second device to third lanes of the third device to yield enabled lanes. The system also include a number of the enabled lanes is less than or equal to a number of the third lanes, and the switch is configured to route the enabled lanes associated with the first device to a first portion of the third lanes in an increasing order and to route the enabled lanes associated with the second device to a second portion of the third lanes in a decreasing order.