Feedback
Settings

Settings

Goto Application

1. US20160027519 - Bitline regulator for high speed flash memory system

PermaLink
Office United States of America
Application Number 14486673
Application Date 15.09.2014
Publication Number 20160027519
Publication Date 28.01.2016
Grant Number 09378834
Grant Date 28.06.2016
Publication Kind B2
IPC
G11C 16/06
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
G11C 16/24
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
24Bit-line control circuits
G11C 29/02
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 29/28
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
04Detection or location of defective memory elements
08Functional testing, e.g. testing during refresh, power-on self testing or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing
18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
26Accessing multiple arrays
28Dependent multiple arrays, e.g. multi-bit arrays
G11C 16/28
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
26Sensing or reading circuits; Data output circuits
28using differential sensing or reference cells, e.g. dummy cells
G11C 29/12
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
04Detection or location of defective memory elements
08Functional testing, e.g. testing during refresh, power-on self testing or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing
CPC
G11C 5/145
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
14Power supply arrangements
145Applications of charge pumps
G11C 5/147
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
14Power supply arrangements
147Voltage reference generators, voltage and current regulators
G11C 7/04
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
04with means for avoiding disturbances due to temperature effects
G11C 7/1048
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1048Data bus control circuits, e.g. precharging, presetting, equalising
G11C 7/12
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 16/24
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
24Bit-line control circuits
Applicants Silicon Storage Technology, Inc.
Inventors Xiaozhou Qian
Yao Zhou
Bin Sheng
Jiaxu Peng
Yaohua Zhu
Agents DLA Piper LLP (US)
Priority Data 201410429526.1 22.07.2014 CN
Title
(EN) Bitline regulator for high speed flash memory system
front page image
Abstract
(EN)

A bitline regulator for use in a high speed flash memory system is disclosed. The bitline regulator is responsive to a set of trim bits that are generated by comparing the bias voltage of a bitline to a reference voltage.
Also published as
CN105336369
KR1020170024127
EP3172732
WO/2016/014164
JP2017527940
# -