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1. (US20110078342) Direct memory access with striding across memory

Office : United States of America
Application Number: 12569173 Application Date: 29.09.2009
Publication Number: 20110078342 Publication Date: 31.03.2011
Grant Number: 08255593 Grant Date: 28.08.2012
Publication Kind : B2
IPC:
G06F 13/28
G06F 13/00
G06F 9/26
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
20
for access to input/output bus
28
using burst mode transfer, e.g. direct memory access, cycle steal
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
22
Micro-control or micro-programme arrangements
26
Address formation of the next micro-instruction
Applicants: Oracle America, Inc.
Inventors: Siddabathuni Ajoy C.
Srinivasan Arvind
Agents: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
Priority Data:
Title: (EN) Direct memory access with striding across memory
Abstract: front page image
(EN)

A DMA device may include an offset determination unit configured to determine a first offset for a DMA transfer and a data transfer unit. The data transfer unit may be configured to receive a first buffer starting address identifying a starting location of a first buffer allocated in memory for the DMA transfer and to generate a first buffer offset address by applying the first offset to the first buffer starting address. The data transfer unit may be further configured to use the first buffer offset address as a starting location in the first buffer for data transferred in the DMA transfer. By applying various offsets, such DMA devices may spread memory access workload across multiple memory controllers, thereby achieving better workload balance and performance in the memory system.