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1. (US20100185830) Logical address offset in response to detecting a memory formatting operation

Office : United States of America
Application Number: 12356765 Application Date: 21.01.2009
Publication Number: 20100185830 Publication Date: 22.07.2010
Grant Number: 08180995 Grant Date: 15.05.2012
Publication Kind : B2
IPC:
G06F 12/10
G06F 12/00
G06F 12/02
G06F 12/08
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
08
in hierarchically structured memory systems, e.g. virtual memory systems
10
Address translation
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
08
in hierarchically structured memory systems, e.g. virtual memory systems
Applicants: Micron Technology, Inc.
Inventors: Asnaashari Mehdi
Benson William E.
Agents: Brooks, Cameron & Huebsch, PLLC
Priority Data:
Title: (EN) Logical address offset in response to detecting a memory formatting operation
Abstract: front page image
(EN)

The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address.