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1. JP2017527940 - 高速フラッシュメモリシステム用のビット線レギュレータ

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Office Japan
Application Number 2017503143
Application Date 10.06.2015
Publication Number 2017527940
Publication Date 21.09.2017
Grant Number 6225293
Grant Date 13.10.2017
Publication Kind B2
IPC
G11C 16/30
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
30Power supply circuits
G11C 5/14
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
14Power supply arrangements
G11C 7/12
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 16/24
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
24Bit-line control circuits
CPC
G11C 5/145
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
14Power supply arrangements
145Applications of charge pumps
G11C 5/147
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
14Power supply arrangements
147Voltage reference generators, voltage and current regulators
G11C 7/04
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
04with means for avoiding disturbances due to temperature effects
G11C 7/1048
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1048Data bus control circuits, e.g. precharging, presetting, equalising
G11C 7/12
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 16/24
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
24Bit-line control circuits
Applicants シリコン　ストーリッジ　テクノロージー　インコーポレイテッド
Inventors チャン　シャオチョウ
ヂョウ　ヤオ
シェン　ビン
ペン　ジャシュ
ヂュー　ヤオホワ
Agents 西島　孝喜
弟子丸　健
田中　伸一郎
大塚　文昭
須田　洋之
上杉　浩
近藤　直樹
岩崎　吉信
Priority Data 201410429526.1 22.07.2014 CN
14486673 15.09.2014 US
Title
(JA) 高速フラッシュメモリシステム用のビット線レギュレータ
Abstract
(JA)

高速フラッシュメモリシステムで使用するためのビット線レギュレータを開示する。このビット線レギュレータは、ビット線のバイアス電圧を基準電圧と比較することによって生成される一連のトリムビットに応答する。
Also published as
CN105336369
US20160027519
KR1020170024127
EP3172732
WO/2016/014164
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