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1. (JP2004342126) INCREASING MEMORY PERFORMANCE IN FLASH MEMORY DEVICE BY SIMULTANEOUSLY WRITING SECTORS TO MULTIPLE DEVICES

Office : Japan
Application Number: 2004199902 Application Date: 06.07.2004
Publication Number: 2004342126 Publication Date: 02.12.2004
Grant Number: 3944496 Grant Date: 11.07.2007
Publication Kind : B2
IPC:
G06F 12/6
G06F 3/6
G06F 3/8
G06F 12/0
G06F 12/2
G11C 16/8
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
06
Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
08
from or to individual record carriers, e.g. punched card
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
08
Address circuits; Decoders; Word-line control circuits
Applicants: LEXAR MEDIA INC
レクサー・メディア・インコーポレイテッド; アメリカ合衆国 94538 カリフォルニア州 フレモント、ベイサイド・パークウェイ 47421番
Inventors: ESTAKHRI PETRO
ペトロ エスタキリ
IMAN BERHANU
ベルハヌ イマン
Priority Data: 3069798 25.02.1998 US
Title: (EN) INCREASING MEMORY PERFORMANCE IN FLASH MEMORY DEVICE BY SIMULTANEOUSLY WRITING SECTORS TO MULTIPLE DEVICES
(JA) 複数のデバイスへ同時書き込み操作を行うことにより高まるフラッシュメモリデバイスにおけるメモリ性能
Abstract:
(EN) PROBLEM TO BE SOLVED: To provide a digital system which has the entire performance increased and has the manufacturing expenses reduced, by adopting a non-volatile memory for storage of digital information organized in a sector format in order to shorten the time required for read and write operations.

SOLUTION: A controller transfers information organized in sectors, each of which includes a user data portion and an overhead portion between a host and a non-volatile memory bank, and simultaneously stores and reads two-byte sectors relating to the same sector in two non-volatile memory devices. Each non-volatile memory device is defined by a row of memory locations wherein corresponding rows of at least two semiconductor devices maintain of two sectors of information therein together with overhead information relating to the two sectors maintained in one of memory rows of the non-volatile memory device.

COPYRIGHT: (C)2005,JPO&NCIPI
(JA)


【課題】 読み出しおよび書き込み操作を行う際にかかる時間を短縮するために、非揮発性メモリをセクタフォーマットで組織化されたデジタル情報の記憶用に採用し、それによりシステムの全体的な性能を上げ、同時にこのデジタルシステムの製造経費を削減する、デジタルシステムを提供する
【解決手段】コントローラはセクタ単位に構成された情報を転送し、各セクタはホストと不揮発性メモリバンクとの間にユーザデータ部分およびオーバーヘッド部分を含み、2つの不揮発性メモリデバイス内の同じセクタに関連する2バイトのセクタの記憶および読み出しを同時に行う。
各不揮発性メモリデバイスは、メモリロケーションの行によって規定され、ここで、少なくとも2つの半導体デバイスの対応する行が、その内部に2セクタの情報を、不揮発性メモリデバイスのメモリ行の1つに維持された2つのセクタに関連するオーバーヘッド情報と共に維持する。
【選択図】 図6