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1. (JP2000510634 ) 複数のデバイスへ同時書き込み操作を行うことにより高まるフラッシュメモリデバイスにおけるメモリ性能

Office : Japan
Application Number: 54391299T Application Date: 25.02.1999
Publication Number: 2000510634 Publication Date: 15.08.2000
Grant Number: 3792259 Grant Date: 05.07.2006
Publication Kind : B2
Prior PCT appl.: Application Number:WOUS1999004247 ; Publication Number:WO1999044113 Click to see the data
IPC:
G06F 12/6
G06F 3/6
G06F 3/8
G06F 12/0
G06F 12/2
G11C 16/8
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
06
Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
08
from or to individual record carriers, e.g. punched card
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
08
Address circuits; Decoders; Word-line control circuits
Applicants: レクサー メディア, インコーポレイテッド; ?アメリカ合衆国 カリフォルニア 94538, フレモント, ベイサイド パークウェイ 47421??s
Inventors: エスタキリ, ペトロ
イマン, ベルハヌ
Priority Data: 3069798 25.02.1998 US
US9904247 25.02.1999 WO
Title: (JA) 複数のデバイスへ同時書き込み操作を行うことにより高まるフラッシュメモリデバイスにおけるメモリ性能
Abstract: front page image
Also published as:
EP0983550EP2306321AU1999029750WO/1999/044113