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1. (EP2382547) LOGICAL ADDRESS OFFSET

Office : European Patent Office
Application Number: 10738832 Application Date: 15.01.2010
Publication Number: 2382547 Publication Date: 02.11.2011
Publication Kind : B1
Designated States: AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR
Prior PCT appl.: Application Number:US2010000095 ; Publication Number: Click to see the data
IPC:
G06F 12/06
G06F 3/06
G06F 12/02
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
06
Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
CPC:
G06F 12/06
G06F 3/0608
G06F 3/0638
G06F 3/0679
G06F 12/0246
G06F 2212/7202
Applicants: MICRON TECHNOLOGY INC
Inventors: ASNAASHARI MEHDI
BENSON WILLIAM E
Priority Data: 2010000095 15.01.2010 US
35676509 21.01.2009 US
Title: (DE) LOGISCHER ADRESSENVERSATZ
(EN) LOGICAL ADDRESS OFFSET
(FR) DÉCALAGE D'ADRESSE LOGIQUE
Abstract: front page image
(EN) The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address.
(FR) La présente invention concerne des procédés, des dispositifs et des systèmes de décalage d'adresse logique. Un mode de réalisation d'un procédé selon l'invention comporte une étape consistant à détecter une opération de formatage d'une unité de mémoire. Ensuite, en réponse à la détection de l'opération de formatage, le procédé comporte les étapes consistant à examiner des informations de format sur l'unité de mémoire, à calculer un décalage d'adresse logique et à appliquer le décalage à une adresse logique d'hôte.
Also published as:
JP2012515954CN102292712KR1020110107856KR1020140016430CN107273058WO/2010/090696