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1. CN102184894 - Semiconductor device and forming method thereof, vertical double diffused metal oxide semiconductor (VDMOS) transistor and forming method of VDMOS transistor

Office China
Application Number 201110103208.2
Application Date 22.04.2011
Publication Number 102184894
Publication Date 14.09.2011
Grant Number
Grant Date 01.04.2015
Publication Kind B
IPC
H01L 21/8234
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
H01L 27/088
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
08including only semiconductor components of a single kind
085including field-effect components only
088the components being field-effect transistors with insulated gate
H01L 21/336
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
336with an insulated gate
H01L 29/78
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
H01L 29/06
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Applicants 上海华虹宏力半导体制造有限公司
Inventors 苟鸿雁
Agents 北京集佳知识产权代理有限公司 11227
Title
(EN) Semiconductor device and forming method thereof, vertical double diffused metal oxide semiconductor (VDMOS) transistor and forming method of VDMOS transistor
(ZH) 半导体器件及形成方法、VDMOS晶体管及形成方法
Abstract
(EN)
The invention discloses a semiconductor device and a forming method thereof, a vertical double diffused metal oxide semiconductor (VDMOS) transistor and a forming method of the VDMOS transistor. The forming method of the semiconductor device comprises the following steps of: providing a semiconductor substrate, wherein the semiconductor substrate comprises a core device area and a marginal area, and an epitaxial layer is formed on the semiconductor substrate; forming a gate dielectric layer and a polysilicon layer on the epitaxial layer in sequence; etching the polysilicon layer and the gate dielectric layer until the epitaxial layer is exposed to form a polysilicon gate, wherein the width of the polysilicon gate adjacent to the marginal area is minimum; performing ion implantation on the semiconductor substrate by taking the polysilicon gate as a mask; and forming a well area in the epitaxial layer between the polysilicon gates, wherein a distance between the two adjacent well areas is a node distance, and the node distance closest to the marginal area is minimum. By the semiconductor device and the forming method thereof, the VDMOS transistor and the forming method of the VDMOS transistor, the breakdown voltage can be effectively prevented on the sub-marginal well area, so that the voltage endurance capability of the overall semiconductor device is improved.

(ZH)

一种半导体器件及其形成方法、VDMOS晶体管及形成方法。其中半导体器件的形成方法,包括如下步骤:提供半导体衬底,所述半导体衬底包括核心器件区和边缘区,所述半导体衬底上形成有外延层;在所述外延层上依次形成栅介质层和多晶硅层;刻蚀多晶硅层和栅介质层至露出所述外延层,形成多晶硅栅极,靠近边缘区的多晶硅栅极宽度最小;以所述多晶硅栅极为掩膜,对半导体衬底进行离子注入,在多晶硅栅极之间的外延层内形成阱区,所述相邻两阱区之间的距离为结距,所述最靠近边缘区的结距最短。本发明所述半导体器件结构及其形成方法、VDMOS晶体管及形成方法可以有效防止击穿电压发生在次边缘的阱区上,从而提高整个半导体器件的耐压能力。