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1. CN101017819 - A protection circuit for constructing ESD release channel with the polycrystalline silicon

Office China
Application Number 200710067517.2
Application Date 05.03.2007
Publication Number 101017819
Publication Date 15.08.2007
Grant Number 100470804
Grant Date 18.03.2009
Publication Kind C
IPC
H01L 27/02
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 23/60
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for
60Protection against electrostatic charges or discharges, e.g. Faraday shields
Applicants Zhejiang University
浙江大学
Inventors Han Yan
韩雁
Cui Qiang
崔强
Dong Shurong
董树荣
Huo Mingxu
霍明旭
Huang Dahai
黄大海
Du Yuchan
杜宇禅
Zeng Caifu
曾才赋
Hong Hui
洪慧
Chen Ming
陈茗
Du Xiaoyang
杜晓阳
Si Ruijun
斯瑞珺
Zhang Jihao
张吉皓
Agents zhangfa gao
杭州求是专利事务所有限公司
Title
(EN) A protection circuit for constructing ESD release channel with the polycrystalline silicon
(ZH) 一种利用多晶硅构建ESD泄放通道的防护电路
Abstract
(EN)
The related static discharge protection circuit comprises: based on current SCR, setting a multicrysta silicon layer and a SiO2 layer between the last layer and trap area, a P+ and N+ multicrystal injection area on sides of the silicon layer, and an intrinsic multicrystal silicon area on midst. This invention sets throughole on two layers and STI on trap area corresponding to the throughhole, arranges a N+ injection area in the STI, equal to the parallel connection of a P-I-N or N-I-P mutlicrystal silicon and a SCR, improves protection capacity, and convenient to adjust the trigger voltage of this protection circuit.

(ZH)

本发明涉及一种静电放电防护电路。现有的可控硅SCR防静电的效果不理想,触发点电压值不能够灵活调整。本发明在现有的可控硅SCR上设置有多晶硅层,多晶硅层与阱区之间设置SiO2氧化层,多晶硅层两边为P+多晶硅注入区和N+多晶硅注入区,中间为本征多晶硅区。本征多晶硅区和SiO2氧化层上打有通孔,阱区上对应通孔的位置设置有环形浅壕沟隔离STI,环形浅壕沟隔离STI内设置N+注入区。采用本发明结构,相当于一个P-I-N或N-I-P结构的多晶硅和传统的可控硅SCR并联,提高了静电防护的性能,同时可以通过改变本征多晶硅的长度调整P-I-N或N-I-P结构的触发电压值,进而灵活调整该防护电路的触发电压值。