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1. WO2023272889 - SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR

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Publication Number WO/2023/272889
Publication Date 05.01.2023
International Application No. PCT/CN2021/112198
International Filing Date 12.08.2021
IPC
H01L 27/24 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
24including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 21/82 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 27/108 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
CPC
H01L 27/10805
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10805with one-transistor one-capacitor memory cells
H01L 27/1085
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10844Multistep manufacturing methods
10847for structures comprising one transistor one-capacitor memory cells
1085with at least one step of making the capacitor or connections thereto
H01L 28/60
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
28Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
40Capacitors
60Electrodes
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 吴玉雷 WU, Yulei
  • 杨彬 YANG, Bin
Agents
  • 北京名华博信知识产权代理有限公司 BOXIN CHINA INTELLECTUAL PROPERTY
Priority Data
202110753746.X02.07.2021CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
(FR) STRUCTURE SEMI-CONDUCTRICE ET SON PROCÉDÉ DE FABRICATION
(ZH) 半导体结构及其制作方法
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Abstract
(EN) Provided in the present disclosure are a method for manufacturing a semiconductor structure, and a semiconductor structure. The method for manufacturing a semiconductor structure comprises: forming a capacitive post in an initial structure; removing part of the initial structure to form a trench, wherein the trench exposes part of a side wall of the capacitive post and a substrate of the initial structure; forming a dielectric layer, wherein the dielectric layer at least covers an exposed surface of the capacitive post; forming a first upper electrode, wherein the first upper electrode covers a surface of the dielectric layer; and forming a second upper electrode, wherein the second upper electrode covers a surface of the first upper electrode. In the axial direction of the capacitive post, the portions of the second upper electrode that are formed in the trench are discontinuous, and the discontinuous portions of the second upper electrode form air gaps.
(FR) Selon des modes de réalisation, la présente divulgation concerne un procédé de fabrication d'une structure semi-conductrice, et une structure semi-conductrice. Le procédé de fabrication d'une structure semi-conductrice comprend les étapes consistant à : former une borne capacitive dans une structure initiale ; retirer une partie de la structure initiale pour former une tranchée, la tranchée exposant une partie d'une paroi latérale de la borne capacitive et un substrat de la structure initiale ; former une couche diélectrique, la couche diélectrique recouvrant au moins une surface exposée de la borne capacitive ; former une première électrode supérieure, la première électrode supérieure recouvrant une surface de la couche diélectrique ; et former une deuxième électrode supérieure, la deuxième électrode supérieure recouvrant une surface de la première électrode supérieure. Dans la direction axiale de la borne capacitive, les parties de la deuxième électrode supérieure qui sont formées dans la tranchée sont discontinues, et les parties discontinues de la deuxième électrode supérieure forment des entrefers.
(ZH) 本公开提供一种半导体结构的制作方法及半导体结构，半导体结构的制作方法包括：在初始结构中形成电容柱；去除部分初始结构形成沟槽，沟槽暴露出电容柱的部分侧壁以及初始结构的衬底；形成介电层，介电层至少覆盖电容柱暴露的表面；形成第一上电极，第一上电极覆盖介电层的表面；形成第二上电极，第二上电极覆盖第一上电极的表面；在电容柱轴向方向上，形成于沟槽内的第二上电极部分不连续，且第二上电极的不连续部分形成空气隙。
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