Processing

Please wait...

Settings

Settings

Goto Application

1. WO2023272627 - THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

Publication Number WO/2023/272627
Publication Date 05.01.2023
International Application No. PCT/CN2021/103767
International Filing Date 30.06.2021
IPC
G11C 19/28 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
19Digital stores in which the information is moved stepwise, e.g. shift registers
28using semiconductor elements
CPC
H01L 2224/08145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
07Structure, shape, material or disposition of the bonding areas after the connecting process
08of an individual bonding area
081Disposition
0812the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
08135the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
08145the bodies being stacked
H01L 2224/80895
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
80001by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
808Bonding techniques
80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
80895between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
H01L 2224/80896
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
80001by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
808Bonding techniques
80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
80896between electrically insulating surfaces, e.g. oxide or nitride layers
H01L 24/08
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas
07Structure, shape, material or disposition of the bonding areas after the connecting process
08of an individual bonding area
H01L 24/80
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
H01L 25/0657
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; ; Multistep manufacturing processes thereof
03all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/00
0657Stacked arrangements of devices
Applicants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventors
  • CHEN, Liang
  • LIU, Wei
  • WANG, Yanhong
  • XIA, Zhiliang
  • ZHOU, Wenxi
  • ZHANG, Kun
  • YANG, Yuancheng
Agents
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Priority Data
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME
(FR) DISPOSITIFS DE MÉMOIRE TRIDIMENSIONNELS ET LEURS PROCÉDÉS DE FORMATION
Abstract
(EN) In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The second semiconductor layer is between the first bonding interface and the first peripheral circuit. The second peripheral circuit is between the second bonding interface and the third semiconductor layer.
(FR) Selon certains aspects, un dispositif de mémoire tridimensionnel (3D) comprend une première structure semi-conductrice, une seconde structure semi-conductrice, une troisième structure semi-conductrice, une première interface de liaison entre la première structure semi-conductrice et la seconde structure semi-conductrice, et une seconde interface de liaison entre la seconde structure semi-conductrice et la troisième structure semi-conductrice. La première structure semi-conductrice comprend un réseau de chaînes de mémoire NON-ET et une première couche semi-conductrice en contact avec des sources du réseau de chaînes de mémoire NON-ET. La seconde structure semi-conductrice comprend un premier circuit périphérique du réseau de chaînes de mémoire NON-ET comprenant un premier transistor, et une seconde couche semi-conductrice en contact avec le premier transistor. Une troisième structure semi-conductrice comprend un second circuit périphérique du réseau de chaînes de mémoire NON-ET comprenant un second transistor, et une troisième couche semi-conductrice en contact avec le second transistor. La seconde couche semi-conductrice se trouve entre la première interface de liaison et le premier circuit périphérique. Le second circuit périphérique se trouve entre la seconde interface de liaison et la troisième couche semi-conductrice.
Latest bibliographic data on file with the International Bureau