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1. WO2022256220 - MEMORY ADDRESS PROTECTION

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Publication Number WO/2022/256220
Publication Date 08.12.2022
International Application No. PCT/US2022/031068
International Filing Date 26.05.2022
IPC
G06F 11/10 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
CPC
G06F 11/1016
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1012using codes or arrangements adapted for a specific type of error
1016Error in accessing a memory location, i.e. addressing error
G06F 11/1044
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1044with specific ECC/EDC distribution
G06F 11/1048
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1048using arrangements adapted for a specific error detection or correction feature
Applicants
  • MICROCHIP TECHNOLOGY INC. [US]/[US]
Inventors
  • GRAUMANN, Peter John Waldemar
Agents
  • GLASS, Kenneth
Priority Data
63/195,61801.06.2021US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) MEMORY ADDRESS PROTECTION
(FR) PROTECTION D'ADRESSES DE MÉMOIRE
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Abstract
(EN) A method for memory protection includes receiving a burst-write instruction that includes data and a burst-write address. The data are segmented into a plurality of data blocks. One or more bits of the burst-write address, or a hash of the burst-write address are concatenated to respective data blocks to obtain data-and-write-address-bit (DWAB) segments. A SECDED ECC is executed on respective DWAB segments to generate a corresponding plurality of sets of parity bits (DWAB-PB). Respective DWAB-PB are concatenated to the corresponding data block to generate corresponding forward-error-correction (FEC) blocks, none of the FEC blocks including the burst-write address or the hash of the burst-write address. A burst-write command and a respective portion of a respective FEC block is sent to respective memory devices during a plurality of beats until all of the beats of the burst-write have been sent.
(FR) Un procédé de protection de mémoire consiste à recevoir une instruction d'écriture en rafale qui comprend des données et une adresse d'écriture en rafale. Les données sont segmentées en une pluralité de blocs de données. Un ou plusieurs bits de l'adresse d'écriture en rafale, ou un hachage de l'adresse d'écriture en rafale, sont concaténés en blocs de données respectifs pour obtenir des segments à bits de données et d'adresse d'écriture (DWAB). Une opération SECDED ECC est exécutée sur des segments DWAB respectifs pour générer une pluralité correspondante de jeux de bits de parité (DWAB-PB). Les DWAB-PB respectifs sont concaténés pour former le bloc de données correspondant afin de générer des blocs à correction d'erreurs sans voie de retour (FEC) correspondants, aucun des blocs FEC ne comprenant l'adresse d'écriture en rafale ou le hachage de l'adresse d'écriture en rafale. Une commande d'écriture en rafale et une partie respective d'un bloc FEC respectif sont envoyées à des dispositifs de mémoire respectifs pendant une pluralité de battements jusqu'à ce que tous les battements de l'écriture en rafale aient été envoyés.
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