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1. WO2022205713 - STANDBY CIRCUIT ASSIGNMENT METHOD AND APPARATUS, DEVICE, AND MEDIUM

Publication Number WO/2022/205713
Publication Date 06.10.2022
International Application No. PCT/CN2021/109442
International Filing Date 30.07.2021
IPC
G11C 29/12 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
04Detection or location of defective memory elements
08Functional testing, e.g. testing during refresh, power-on self testing or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing
CPC
G11C 2029/1202
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
1202Word line control
G11C 2029/1204
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
1204Bit line control
G11C 29/12
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 陈予郎 CHEN, Yui-lang
Agents
  • 广州华进联合专利商标代理有限公司 ADVANCE CHINA IP LAW OFFICE
Priority Data
202110352509.231.03.2021CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) STANDBY CIRCUIT ASSIGNMENT METHOD AND APPARATUS, DEVICE, AND MEDIUM
(FR) PROCÉDÉ ET APPAREIL D'ATTRIBUTION DE CIRCUIT DE SECOURS, DISPOSITIF, ET SUPPORT
(ZH) 备用电路分派方法、装置、设备及介质
Abstract
(EN) A standby circuit assignment method and apparatus, a device, and a medium. The method comprises: executing a first test item, and obtaining first test data; determining, according to the first test data, a first standby circuit assignment result comprising the number of assigned regional standby circuits and corresponding position data; executing a second test item, and obtaining second test data; when failed bits obtained during the execution of the second test item comprise failed bits outside repair ranges of the assigned regional standby circuits and assigned global standby circuits, and assignable regional standby circuits have been assigned, obtaining target position data of failed bits in a target sub-region and an associated sub-region on the basis of the first test data and the second test data; and determining a second standby circuit assignment result according to the target position data, the first test data and the second test data. Thus, the utilization efficiency of standby circuits and the yield of storage chips are improved.
(FR) L'invention concerne un procédé et un appareil d'attribution de circuit de secours, un dispositif, et un support. Le procédé comprend les étapes suivantes : exécution d'un premier élément de test, et obtention de premières données de test ; détermination, selon les premières données de test, d'un premier résultat d'attribution de circuit de secours comprenant le nombre de circuits de secours régionaux attribués et des données de position correspondantes ; exécution d'un second élément de test, et obtention de secondes données de test ; lorsque des bits défaillants obtenus pendant l'exécution du second élément de test comprennent des bits défaillants en dehors des plages de réparation des circuits de secours régionaux attribués et des circuits de secours globaux attribués, et des circuits de secours régionaux attribuables ont été attribués, obtention de données de position cible de bits défaillants dans une sous-région cible et une sous-région associée sur la base des premières données de test et des secondes données de test ; et détermination d'un second résultat d'attribution de circuit de secours selon les données de position cible, les premières données de test et les secondes données de test. Ainsi, l'efficacité d'utilisation de circuits de secours et le rendement de puces de stockage sont améliorés.
(ZH) 一种备用电路分派方法、装置、设备及介质,所述方法包括:执行第一测试项目,获取第一测试数据;根据第一测试数据确定包括已分派的地域备用电路的数量和对应的位置数据的第一次备用电路分派结果;执行第二测试项目,获取第二测试数据;当执行第二测试项目期间获取的失效位元包括已分派的地域备用电路及已分派的全域备用电路的修补范围之外的失效位元,且已分派完可分派的地域备用电路时,基于第一测试数据和第二测试数据获取处于目标子域及关联子域的失效位元的目标位置数据;根据目标位置数据第一测试数据和第二测试数据确定第二次备用电路分派结果,以提高备用电路的利用效率及存储芯片良率。
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