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1. WO2022205701 - SEMICONDUCTOR STRUCTURE PREPARATION METHOD AND SEMICONDUCTOR STRUCTURE

Publication Number WO/2022/205701
Publication Date 06.10.2022
International Application No. PCT/CN2021/108815
International Filing Date 28.07.2021
IPC
H01L 21/8242 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
8242Dynamic random access memory structures (DRAM)
H01L 27/108 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
CPC
H01L 27/10805
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10805with one-transistor one-capacitor memory cells
H01L 27/10888
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10844Multistep manufacturing methods
10847for structures comprising one transistor one-capacitor memory cells
10882with at least one step of making a data line
10888with at least one step of making a bit line contact
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 冯大伟 FENG, Dawei
Agents
  • 北京同立钧成知识产权代理有限公司 LEADER PATENT & TRADEMARK FIRM
Priority Data
202110342487.130.03.2021CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) SEMICONDUCTOR STRUCTURE PREPARATION METHOD AND SEMICONDUCTOR STRUCTURE
(FR) PROCÉDÉ DE PRÉPARATION DE STRUCTURE SEMI-CONDUCTRICE ET STRUCTURE SEMI-CONDUCTRICE
(ZH) 半导体结构的制备方法及半导体结构
Abstract
(EN) The present application relates to the technical field of semiconductors. Provided are a semiconductor structure preparation method and a semiconductor structure. The semiconductor structure preparation method comprises: providing a substrate; on the substrate, sequentially stacking and forming a bit line contact layer, a first mask layer, a second mask layer and a plurality of mask structures arranged at intervals, wherein a first opening is formed between adjacent mask structures; and removing part of the second mask layer that is exposed in the first opening, so as to form a first groove in the second mask layer. According to the present application, part of a second mask layer is thinned by using a first groove, such that when the second mask layer is etched, since the thickness of the second mask layer is reduced, the time needed for etching the second mask layer is shortened, thereby avoiding side-etching of the second mask layer, preventing the loss of a bit line contact structure, and improving the storage performance of a semiconductor structure.
(FR) La présente demande se rapporte au domaine technique des semi-conducteurs. La demande concerne un procédé de préparation de structure semi-conductrice et une structure semi-conductrice. Le procédé de préparation de structure semi-conductrice consiste à : utiliser un substrat ; sur le substrat, empiler séquentiellement et former une couche de contact de ligne de bits, une première couche de masque, une seconde couche de masque et une pluralité de structures de masque disposées à intervalles, une première ouverture étant formée entre des structures de masque adjacentes ; et retirer une partie de la seconde couche de masque qui est apparente dans la première ouverture, de façon à former une première rainure dans la seconde couche de masque. Selon la présente demande, une partie d'une seconde couche de masque est amincie au moyen d'une première rainure, de telle sorte que, lorsque la seconde couche de masque est gravée, étant donné que l'épaisseur de la seconde couche de masque est réduite, le temps nécessaire à la gravure de la seconde couche de masque soit raccourci, ce qui permet d'éviter la gravure latérale de la seconde couche de masque, d'empêcher la perte d'une structure de contact de ligne de bits et d'améliorer les performances de stockage d'une structure semi-conductrice.
(ZH) 本申请提供一种半导体结构的制备方法及半导体结构,涉及半导体技术领域,该半导体结构的制备方法包括:提供基底,在基底上依次层叠形成位线接触层、第一掩膜层、第二掩膜层以及多个间隔设置的掩膜结构,相邻的掩膜结构之间形成第一开口;去除暴露在第一开口内的部分第二掩膜层,以在第二掩膜层内形成第一凹槽。本申请利用第一凹槽减薄部分的第二掩膜层,这样在蚀刻第二掩膜层时,由于第二掩膜层的厚度降低,减少了蚀刻第二掩膜层的时间,进而避免了侧刻蚀第二掩膜层,防止了位线接触结构的缺失,提高了半导体结构的存储性能。
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