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1. WO2022205698 - MASK PATTERN AND PREPARATION METHOD THEREFOR, AND SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREFOR

Publication Number WO/2022/205698
Publication Date 06.10.2022
International Application No. PCT/CN2021/108538
International Filing Date 27.07.2021
IPC
H01L 21/8242 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
8242Dynamic random access memory structures (DRAM)
CPC
H01L 27/108
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
H01L 27/10844
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10844Multistep manufacturing methods
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 宛强 WAN, Qiang
  • 占康澍 ZHAN, Kangshu
  • 夏军 XIA, Jun
  • 李森 LI, Sen
  • 徐朋辉 XU, Penghui
  • 刘涛 LIU, Tao
Agents
  • 广州华进联合专利商标代理有限公司 ADVANCE CHINA IP LAW OFFICE
Priority Data
202110340696.230.03.2021CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) MASK PATTERN AND PREPARATION METHOD THEREFOR, AND SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREFOR
(FR) MOTIF DE MASQUE ET SON PROCÉDÉ DE PRÉPARATION, ET STRUCTURE SEMI-CONDUCTRICE ET SON PROCÉDÉ DE PRÉPARATION
(ZH) 掩膜图形、半导体结构及其制作方法
Abstract
(EN) The present application relates to a preparation method for a mask pattern, comprising: forming a pattern transfer layer, an etch stop layer, a sacrificial layer, and a hard mask layer which are stacked from bottom to top; patterning the hard mask layer and the sacrificial layer to obtain a sacrificial pattern, the sacrificial pattern exposing the etch stop layer; forming sidewall structures on the sidewalls of the sacrificial pattern; removing the sacrificial pattern; forming a filling layer between the sidewall structures, the etching selection ratio of the sidewall structures to the filling layer being greater than 100; removing the sidewall structures to form an initial mask pattern; and etching the etch stop layer and the pattern transfer layer on the basis of the initial mask pattern to transfer the pattern of the initial mask pattern to the pattern transfer layer to obtain a target mask pattern.
(FR) La présente demande concerne un procédé de préparation de motif de masque, comprenant : la formation d'une couche de transfert de motif, d'une couche d'arrêt de gravure, d'une couche sacrificielle et d'une couche de masque dur qui sont empilées de bas en haut ; la formation de motifs sur la couche de masque dur et la couche sacrificielle pour obtenir un motif sacrificiel, le motif sacrificiel exposant la couche d'arrêt de gravure ; la formation de structures de paroi latérale sur les parois latérales du motif sacrificiel ; l'élimination du motif sacrificiel ; la formation d'une couche de remplissage entre les structures de paroi latérale, le rapport de sélection de gravure des structures de paroi latérale à la couche de remplissage étant supérieur à 100 ; l'élimination des structures de paroi latérale pour former un motif de masque initial ; et la gravure de la couche d'arrêt de gravure et de la couche de transfert de motif sur la base du motif de masque initial pour transférer le motif du motif de masque initial à la couche de transfert de motif pour obtenir un motif de masque cible.
(ZH) 本申请涉及一种掩膜图形的制作方法,包括:形成由下至上叠置的图形转移层、刻蚀停止层、牺牲层及硬掩膜层;图形化硬掩膜层及牺牲层,以得到牺牲图形,牺牲图形暴露出刻蚀停止层;于牺牲图形的侧壁形成侧墙结构;去除牺牲图形;于侧墙结构之间形成填充层,侧墙结构与填充层的刻蚀选择比大于100;去除侧墙结构,以形成初始掩膜图形;基于初始掩膜图形刻蚀刻蚀停止层及图形转移层,以将初始掩膜图形的图案转移至图形转移层,以得到目标掩膜图形。
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