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1. WO2022205691 - SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREFOR

Publication Number WO/2022/205691
Publication Date 06.10.2022
International Application No. PCT/CN2021/107740
International Filing Date 22.07.2021
IPC
H01L 21/8242 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
8242Dynamic random access memory structures (DRAM)
H01L 27/108 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
CPC
H01L 27/10805
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10805with one-transistor one-capacitor memory cells
H01L 27/10891
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10844Multistep manufacturing methods
10847for structures comprising one transistor one-capacitor memory cells
10882with at least one step of making a data line
10891with at least one step of making a word line
Applicants
  • 长鑫存储技术有限公司 CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • 于业笑 YU, Yexiao
Agents
  • 广州华进联合专利商标代理有限公司 ADVANCE CHINA IP LAW OFFICE
Priority Data
202110351087.731.03.2021CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREFOR
(FR) STRUCTURE SEMI-CONDUCTRICE ET SON PROCÉDÉ DE PRÉPARATION
(ZH) 半导体结构及其制备方法
Abstract
(EN) The present application relates to a semiconductor structure and a preparation method therefor. The method comprises: providing a substrate; forming an initial trench in the substrate; forming a sacrificial layer, wherein the sacrificial layer comprises a first portion and a second portion, with the first portion filling the initial trench, and the second portion covering the upper surface of the substrate and the upper surface of the first portion; forming a segmentation groove in the second portion, so as to pattern the second portion into a sacrificial pattern, wherein the sacrificial pattern is disposed corresponding to the first portion; forming a filling layer in the segmentation groove, wherein the filling layer fills the segmentation groove; removing the sacrificial pattern and the first portion, so as to form a word-line trench; and forming a buried-type gate word line in the word-line trench.
(FR) L'invention concerne une structure semi-conductrice et son procédé de préparation. Le procédé comprend les étapes consistant à : fournir un substrat ; former une tranchée initiale dans le substrat ; former une couche sacrificielle, la couche sacrificielle comprenant une première partie et une deuxième partie, la première partie remplissant la tranchée initiale, et la deuxième partie recouvrant la surface supérieure du substrat et la surface supérieure de la première partie ; former une rainure de segmentation dans la deuxième partie, de manière à former un motif de la deuxième partie en un motif sacrificiel, le motif sacrificiel étant situé selon la première partie ; former une couche de remplissage dans la rainure de segmentation, la couche de remplissage remplissant la rainure de segmentation ; retirer le motif sacrificiel et la première partie, de manière à former une tranchée de ligne de mots ; et former une ligne de mots de grille de type enterrée dans la tranchée de ligne de mots.
(ZH) 本申请涉及一种半导体结构及其制备方法,包括:提供基底;于基底内形成初始沟槽;形成牺牲层,牺牲层包括第一部分及第二部分;第一部分填满初始沟槽,第二部分覆盖基底的上表面及第一部分的上表面;于第二部分内形成分割槽,以将第二部分图形化为牺牲图形,牺牲图形与第一部分对应设置;于分割槽内形成填充层,填充层填满分割槽;去除牺牲图形及第一部分,以形成字线沟槽;于字线沟槽内形成埋入式栅极字线。
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